Semiconductor topography employing a shallow trench isolation st

Details Semiconductor topography employing a shallow trench isolation st Semiconductor topography employing a shallow trench isolation st

1999-01-26

2000-12-26

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438248, 438424, 438431, H01L 21311

Patent

active

061659061

ABSTRACT:
A method of forming an improved isolation trench between active regions within the semiconductor substrate involves oxidizing unmasked portions of a semiconductor substrate prior to etching an isolation trench into the semiconductor substrate. By oxidizing the unmasked portions of the semiconductor prior to etching, an isolation trench with rounded corners may be formed.

REFERENCES:
patent: 5741738 (1998-04-01), Mandelman et al.
patent: 5753561 (1998-05-01), Lee et al.
patent: 5801083 (1998-09-01), Yu et al.
patent: 5989977 (1999-11-01), Wu
patent: 6001704 (1999-12-01), Cheng et al.
patent: 6008079 (1999-12-01), Wu

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