Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
2000-09-08
2003-04-15
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S487000, C438S488000, C438S503000
Reexamination Certificate
active
06548380
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates, among others, to a semiconductor thin film used as a semiconductor element, a method for manufacturing the same, and a thin film transistor employing the same.
(2) Description of the Prior Art
Amorphous silicon thin films are conventionally being employed as functional semiconductor thin films for use in thin film semiconductor devices such as thin film transistors or thin film solar batteries. Thin film transistors employing amorphous silicon films as active layers are being materialized as switching elements for driving pixels in liquid crystal display devices or the like, and solar batteries employing amorphous silicon films as photoelectric converting layers are being materialized in consumer-oriented fields such as watches/clocks or calculators.
Transistors that are employed in liquid crystal displays of active matrix type are, for instance, transistors for switching respective pixels or high-mobility transistors for peripheral circuits for sending control signals, which are based on image information to be displayed, to respective pixel transistors. Among these, it was conventionally the case that TFTs using amorphous silicon hydride (a-Si:H) as active layers in pixel transistors while these TFTs were manufactured through plasma chemical vapor deposition (PCVD).
While such a-Si:H TFTs are advantaged in that they may be manufactured at a temperature of approximately 300° C. in which light-transmitting glass substrates of low costs are well applicable, drawbacks are presented in that the mobility of n-type TFTs will be small ranging around 1 cm
2
/Vs while no practical mobility can be achieved in case of p-type TFTs so that such TFTs are not applicable to peripheral circuits. Thus, peripheral circuits were arranged by mounting IC chips onto substrates.
On the other hand, TFTs employing polycrystalline silicon (poly-Si) as active layers are advantaged in that these TFTs exhibit high mobility for both, n-type and p-type ones and that they are applicable also to peripheral circuits. However, when using poly-Si, it is necessary to form films through reduced-pressure CVD methods in which processes need to be performed in high-temperature conditions of not less than 600° C. and thus to present a drawback that glass substrates of low costs could not be used.
Active research and developments related to techniques of manufacturing poly-Si (low temperature poly-Si) at low temperature in which glass substrates of low costs applicable are being made and materialized. One exemplary method is a method for manufacturing a polycrystalline film in which excimer laser beams with wavelengths existing in ultraviolet regions that are extremely highly absorbed by a-Si:H films are being irradiated onto a-Si:H films in a pulse-like manner for rapidly performing heat-melting and cooling of the a-Si:H film to achieve recrystallization (see Japanese Patent No. 2725669 and others). While this method enables it to form TFTs of high mobility at low temperature of not more than 600° C. in which glass substrates are applicable, drawbacks of this method reside in the fact that it is difficult to form poly-Si films of large areas owing to the fact of utilizing laser beams, and that the productivity thereof will be inferior. Further, since a-Si:H films generally contain hydrogen of not less than 10 atom %, bumping of hydrogen will be caused through rapid heating using excimer laser beams to result in peeling of films or roughing of surfaces when using the films as they are, and it was necessary to perform an additional heat-treatment process of preliminarily removing hydrogen contained in the film.
It has been proposed for a technique for solving the above subjects as will be explained below as a technique of manufacturing crystalline silicon films at low temperature.
Japanese Patent Unexamined Publication No. 8-250438 (1996) discloses a method for forming a silicon thin film through catalytic CVD methods in which a catalyst is heated to not less than a melting point of Si, in which a part of molecules of a raw material gas is made to contact the heated catalyst for resolution, and in which film forming is performed through CVD and crystal growth is performed on a substrate. In this method, a part of fly-coming species will reach quite a high temperature, behave as if the substrate surface would be of high temperature, and it is considered that the polycrystalline silicon is formed at a low substrate temperature. Actually, the raw material gas is a mixed gas of silicon (Si) compound gas and other substances and the catalyst is heated through supplied electric power. By setting the following conditions to be suitable for making the silicon thin film that is made from depository species to be a polycrystalline thin film, a polycrystalline silicon thin film is formed on a substrate of low temperature: a pressure condition in which the pressure of a reaction chamber for generating the silicon thin film is set to be at low pressure; a condition for a mixing ratio of raw material gas in which the ratio of gas containing other substances to gas of silicon compounds is set to be larger; and a condition for supplied electric power for the catalyst in which the electric power to be supplied to the catalyst is set to obtain a catalyst temperature that is not less than the melting point of silicon.
A method for forming a crystalline silicon film through chemical vapor deposition process in which resolution is performed through plasma resolution utilizing high-frequency inductive coupled plasma (ICP) and in which the resolved raw material gas is used is disclosed in Japanese Patent Unexamined Publication No. 10-265212 (1998) and No. 11-74204 (1999). In such a method, electric power of high frequency is invested through electrodes (antenna) for generating ICP (reference should be made to “Applied Physics”, Hidero Sugai, Vol. 63, No. 6, 1994, pp. 559-567) for generating high density plasma of the raw material gas and for performing film forming through resolution and high excitation of the raw material gas. It is obvious from the above Japanese Patent Unexamined Publication No. 10-265212 that it is possible to obtain a polycrystalline silicon thin film with a conductivity that is higher by an order of magnitude by setting the high frequency electric power to not less than 800 W while the conductivity of the film is degraded in case the pressure exceeds 6.65 PA (50 mTorr) so that no minor-crystalline or polycrystalline silicon thin film could be obtained.
A method for film forming through plasma CVD in which ion beams are irradiated from the exterior for forming a crystalline silicon film is disclosed in Japanese Patent Unexamined Publication No. 11-145062 (1999). In such a method, surface excitation effects can be obtained by irradiating ion beams of 0.1 kV to 40 kV on to a film forming surface to thereby obtain a silicon thin film exhibiting favorable crystallinity.
However, while it seems to be possible to manufacture crystalline silicon films of minor-crystalline or polycrystalline type at temperatures in which glass substrates are applicable by using the above methods, all of the crystalline silicon films that may be obtained by the above techniques assume crystal structures in which crystals are grown on substrates in columnar styles so that large concaves and convexes are formed on these surfaces as illustrated in FIG.
1
. This is due to the fact that growth of crystalline silicon films is dependent on a balance between film deposition of silicon type radical and etching using hydrogen atoms or halogen type radical. More particularly, since an etching speed within grain boundaries including a large amount of weak Si combinations is faster than an etching speed within the grains, the grain boundaries are selectively etched to expose the grains, and it is considered that concaves and convexes of 20 nm to 100 nm are generated thereby. Such concaves and convexes formed on the surface cause degradations in characteristics and reliabil
Goto Masashi
Nishitani Mikihiko
Terauchi Masaharu
Guerrero Maria
Zarabian Amir
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