Semiconductor testing circuit, semiconductor storage device,...

Details Semiconductor testing circuit, semiconductor storage device,... Semiconductor testing circuit, semiconductor storage device,...

2007-06-05

2007-06-05

Chung, Phuong My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000, C714S706000, C365S201000

Reexamination Certificate

active

10763334

ABSTRACT:
A semiconductor testing circuit being arranged for testing a semiconductor storage device, and having a simple construction and a great number of executable test patterns. Counters designate portions of a write/read address by count values outputted from the counters, respectively, where each of the portions is comprised of one bit or a plurality of successive bits. A switching circuit selectively outputs counter-control signals for individually controlling operations of the counters. Each of the counter-control signals is a common counter-control signal commonly used for the counters or the most significant bit of one of the portions outputted from a first one of the counters other than a second one of the counters for which the counter-control signal is outputted. Thus, it is possible to change assignment of the write/read address to the count values of the counters.

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patent: 5214611 (1993-05-01), Shigehara et al.
patent: 6338154 (2002-01-01), Kim
patent: 2001222900 (2001-08-01), None
patent: 2002163899 (2002-06-01), None

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