Semiconductor testing apparatus and method for optimizing a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique

Reexamination Certificate

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C714S724000

Reexamination Certificate

active

06895548

ABSTRACT:
A semiconductor testing apparatus includes a test program memory for storing a test program, a measuring/deciding section for receiving the test program and supplying a test signal to the semiconductor device with a wait time set to a predetermined value and detecting an optimal value of a wait time, after an elapse of the wait time, based on a response signal outputted from the semiconductor device and effecting an OK/NG decision on the electrical characteristics of the semiconductor device based on a result of the measurement and, if the result of the decision is found to be “NG”, remeasuring the electrical characteristics of the semiconductor device under a newly set wait time and effecting such remeasurement on the electrical characteristics of the semiconductor device at each newly set wait time until the result of such decision becomes “OK”.

REFERENCES:
patent: 6263463 (2001-07-01), Hashimoto
patent: 10-90347 (1998-04-01), None

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