Semiconductor test system and method, and medium for recording t

Details Semiconductor test system and method, and medium for recording t Semiconductor test system and method, and medium for recording t

1997-09-25

1999-11-09

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714711, G11C 2900

Patent

active

059833742

ABSTRACT:
The processing for deciding the remedy as being possible or impossible and the processing for remedying bit fails can be both executed in a short time on the basis of bit mask processing. Fail data are transferred from the tester to the redundancy processor (in Step S101), and the number of the fail addresses stored in the buffer memory is compared with the maximum number of fail bits (in Step S103). Further, the line fail detection and the remedy processing are both executed (in Step S105), and the redundancy processor decides whether the number of the line fails exceeds the number of the spare rows and the number of the spare columns or not (in Step S107). Further, the bit mask processing is executed for the fail addresses (in Step S109) to decide the remedy possibility (in Step S111). Here, the maximum remediable number of the bit mask processings can be calculated on the basis of "the number of row spares R+the number of the column spares". When the number of the bit mask processing exceeds this calculated limit value, the remedy is decided as being impossible (in Step S121), so that any bit fail remedy processing is not more executed at the succeeding stage.

REFERENCES:
patent: 4460997 (1984-07-01), Harns
patent: 4628509 (1986-12-01), Kawaguchi

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