Semiconductor test system

Details Semiconductor test system Semiconductor test system

1999-05-14

2002-04-16

Hoang, Huan (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C714S744000

Reexamination Certificate

active

06374392

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor test system for testing semiconductor devices with high speed, and more particularly, to a semiconductor test system which can operate in a pin multiplex mode to generate test signals higher than two times of more than a repetition rate of a reference clock signal without involving limitations existed in the conventional technology.
BACKGROUND OF THE INVENTION
The semiconductor test system of the present invention is directed to a test system having a function of a pin-multiplex mode. In a pin-multiplex mode, test signals of a plurality of tester channel (test pin) are multiplexed in a time sequential manner so that the test signal of high repetition rate can be generated for testing a semiconductor device. Thus, a pin-multiples mode in the semiconductor test system functions in a manner similar to a parallel-serial conversion process.
Such a pin-multiplex mode is typically performed in a per-pin structured test system. Such a semiconductor test system is also called a per-pin IC tester. Here, a per-pin IC tester refers to a semiconductor test system wherein all of the hardware resource for generating test parameters such as signals are independently provided for each test channel (tester pin) of an IC tester. Consequently, in a per-pin IC tester, various test parameters for a semiconductor devices under test (DUT) can be set independently for each pin of the DUT. Although the present invention is advantageously applicable to the per-pin IC tester, it is also feasible to other types of semiconductor test system such as a shared resource type IC tester.
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals produced by an IC tester at its appropriate tester pins (channels) at predetermined test timings. The IC tester receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device properly performs the intended functions.
Typically, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the IC tester. Generally, the various timings of the tester cycles, test signals and strobe signals are generated based on a reference clock. The reference clock is produced by a high stability oscillator, for example, a crystal oscillator provided in the IC tester. When the required timing resolution in an IC tester is equal to or an integer multiple of the highest clock rate (one clock cycle) of the reference clock oscillator, variety of timing signals can be generated by simply dividing the reference clock by a counter or a divider.
However, IC testers are usually required to have timing resolution higher than the highest clock rate, i.e., the shortest time period, of the reference (system) clock. For example, in the case where a reference clock cycle used in an IC tester is 10 ns (nanosecond), but the IC tester needs to have timing resolution of 0.3 ns or higher, it is not possible to achieve such timing resolution by simply applying or dividing the reference clock.
To generate such timing signals, it is known in the prior art that such timings are described by timing data in a test program. For describing the timings with the resolution higher than the reference clock rate, the timing data is described by a combination of an integer multiple of the reference clock time interval (integral part) and a fraction of the reference clock cycle (fractional part). Such timing data is stored in a timing memory and read out at each cycle of the test cycle. Thus, in each test cycle, test signals and strobe signals are generated with reference to the test cycle, such as a start point of each cycle, based on the timing data.
FIG. 4
is a schematic block diagram showing an example of a conventional semiconductor test system. The example of
FIG. 4
shows a basic configuration of a semiconductor test system having a shared resource structure. A pattern generator
2
generates a test pattern to be provided to a DUT (device under test)
9
and an expected value pattern to be provided to a pattern comparator
7
. A timing generator
3
generates a timing pulse signal to synchronize the timing of the whole system, and provides the timing pulse signal to the pattern generator
2
, the pattern comparator
7
, a wave formatter
4
, an analog comparator
6
.
The timing generator
3
provides the timing pulse (tester rate pulse) and timing data to the wave formatter
4
. Based on the pattern data from the pattern generator
2
and the timing pulse and timing data from the timing generator
3
, the wave formatter
4
forms a test signal having a specified waveform and timings and provides the test signal to a driver
5
. The pattern data is also called format control data (FCDATA) which defines rising and falling edges of the test signal waveform. The timing data (timing set data) defines timings (delay times) of the rising and falling edges of the waveform relative to the test cycle. Although not shown in
FIG. 4
, the wave formatter
4
includes a set/reset flip-flop to form the test signal to be provided to the driver
5
. The driver
5
regulates the amplitude of the test signal to a predetermined level and applies the test signal to the DUT
9
.
A response signal from the DUT
9
is compared with a reference voltage at a predetermined strobe timing by the analog comparator
6
. The resultant logic signal is provided to the pattern comparator
7
wherein a logic comparison is performed between the resultant logic pattern from the analog comparator
6
and the expected-value pattern from the pattern generator
2
. The pattern comparator
7
checks whether two patterns match with each other or not, thereby determining pass or failure of the DUT
9
. When a failure is detected, such fail information is provided to a fail memory
8
and is stored along with the information of the failure address of the DUT
9
from the pattern generator
2
in order to perform failure analysis later.
To generate each signal to perform the foregoing operations, a memory is provided with a data table that stores data in each of the pattern generator
2
, the timing generator
3
, and the wave formatter
4
. The data in the data table is formed by a test program that a user or programmer has produced based on the specifications of the DUT
9
. The test program is provided to each unit in the IC tester from a test processor
1
through a tester bus in FIG.
4
. Thus, the test processor
1
controls an overall operation of the test system based on the test program. In the table of the pattern generator
2
, test pattern data for a plurality of channels is provided, thereby allocating the pattern data to each of the terminal pins
1
-n of the DUT
9
.
The memory in the timing generator
3
includes a rate set table and a clock set table. The rate set table stores the rate data indicating the tester rate or test cycle (may also be referred to as “RATE”). The clock set table stores timing data showing the timings (delay times) of edges in a test signal waveform to be produced by the wave formatter
4
. For example, the delay times are defined with reference to the start point of the test cycle. Such rate data and timing data are provided from the pattern generator
2
to the timing generator
3
prior to the start of the test operation. In contrast, pattern data showing the edges in the test signal waveform is provided in real time to the timing generator
3
.
Thus, the timing generator receives the timing data (timing set data) in advance while it receives the pattern data (format control data FCDATA or edge data) during the operation. Based on the timing data and pattern data, the timing pulse (tester rate pulse) and the timing data are generated by the timing generator
3
which are provided to the wave formatter
4
to form the

Affiliated with

Also associated with

Rating

Semiconductor test system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor test system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor test system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2880313