Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2001-01-04
2003-04-29
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S842000, C029S844000, C029S853000, C324S754090
Reexamination Certificate
active
06553661
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to semiconductor test structures and more particularly to a semiconductor die test carrier that is built with the process of having a laser define the current carrying structures for the interconnection of the IC to the tester.
BACKGROUND OF THE INVENTION
The testing of semiconductor devices is an important part of the design and manufacture of integrated circuits. Many tests, including die and wafer level tests and burn-in tests, are performed during the design and manufacture of semiconductor devices. However, the costs associated with testing these devices are often expensive. In order to control costs of production and costs to the ultimate customer, the costs associated with the design, manufacture and processing of die level and wafer level test and burn-in equipment should be equivalent to or less than the cost per unit to package the integrated circuit die product. Presently, tooling provided for die and wafer level test and burn-in can be two to three times the cost per unit that is represented by packaging. The cost is driven by the expense associated with the micro tooling required to build the interfacing structures to the semiconductor die product. The present tooling process for die and wafer level burn-in structures involves the use of photomasks and plotolithographic processes. These processes are expensive and the tooling can be used for only one version of a semiconductor die product. Typically in the early life of a semiconductor die product there are several revisions that the die product undergoes, e.g. revisions to shrink the overall die size or revisions to accommodate a new package form factor. This means that if a die or wafer tool is built that mirrors the die product at an earlier revision it will become obsolete as soon as the product changes to a newer more advanced revision. The cost associated with reconstructing the die and wafer carrier is just as large as the initial cost bore to interface with the lower die revision. The location of the die bond pads for interconnection to the die carrier changes when such a revision in the silicon takes place. The cost of upgrading the new tooling becomes burdensome to the IC supplier and as a result the suppliers find it more effective to build the entire design and process flows around the packaged product. This limits the form factor that is available to packed parts and thus in the long term limits the packaging options for the IC products. Thus, what is needed is a reliable and low cost tool bare die and wafer level tests and burn-in.
SUMMARY OF THE INVENTION
The present invention discloses a method using a machine-controlled laser to form a test structure that interfaces a semiconductor die to test equipment. The method comprises forming a conductive material layer on a substrate and defining first coordinates on the substrate corresponding to at least one predefined bond pad coordinate on the semiconductor die. The method further comprises defining second coordinates on the substrate corresponding to at least one predefined test equipment contact point location, defining third coordinates on the substrate corresponding to an interconnect between the predefined bond pad and the predefined test equipment contact point location, and ablating portions of the conductive material layer using a laser beam, while leaving unablated portions of the conductive material at the first, second and third coordinates.
One advantage of the present invention is that it eliminates costly customized test carrier structures and provides a low cost alternative that can be easily built. Changing the layout for the features on the test carrier is performed by software control of the laser beam when a new test carrier is to be built.
Because of the ease of changing the electrical conductive traces a new substrate can be built to replace the old and obsolete one that no longer interfaces with the die properly. The time to make the changes for the substrate is as long as it takes to modify the software program that houses the interface coordinates for the die to the test carrier. The cycle time has been reduced from weeks for a photolithography mask to hours for laser driven by software control. The laser can etch lines for substrates that can be easily backfilled into the existing test and burn-in infrastructure. This further helps to reduce the cost of the change over of test substrates.
Another advantage of the present invention is that it can be used throughout the design process for testing the various revisions of a packaged product design. As soon as the design engineer has silicon he is enabled to evaluate the IC that has been built as a single die unit.
A further advantage of the present invention is that S/C suppliers are not constrained to building the entire design and process flows around the packaged product.
REFERENCES:
patent: 4404059 (1983-09-01), Livshits et al.
patent: 4906920 (1990-03-01), Huff et al.
patent: 5180977 (1993-01-01), Huff et al.
patent: 5264787 (1993-11-01), Woith et al.
patent: 5422574 (1995-06-01), Kister
patent: 5583445 (1996-12-01), Mullen
patent: 5643472 (1997-07-01), Engelsberg et al.
patent: 5929521 (1999-07-01), Wark et al.
patent: 6027346 (2000-02-01), Sinsheimer et al.
patent: 6032356 (2000-03-01), Eldridge et al.
patent: 6060891 (2000-05-01), Hembree et al.
patent: 6307387 (2001-10-01), Gleason et al.
patent: 2002/0008529 (2002-01-01), Wilson et al.
Arnold Richard W.
Forster James
Wilson Lester
Arbes Carl J.
Brady III Wade James
Phan Tim
Skrehot Michael K.
Telecky , Jr. Frederick J.
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