Semiconductor test structure for estimating defects at isolation

Details Semiconductor test structure for estimating defects at isolation Semiconductor test structure for estimating defects at isolation

1997-04-08

2000-03-21

Dutton, Brian

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438 18, G01R 3126, H01L 2166

Patent

active

060401990

ABSTRACT:
An A1 pad (11) is provided on a field oxide film isolation (5). The A1 pad (11) is electrically connected to a gate electrode (7) with an A1 wiring pattern (10) and the like. In measurement, a probe (3) comes into contact with the A1 pad (11) to apply a voltage thereto. The probe (3) does not come into direct contact with the gate electrode (7), and therefore no stress is applied to a region below a gate insulation film (6) in which a depletion layer is to be created. With this structure, more accurate result is obtained in a test of estimating defects at an isolation edge using a C-t measurement method.

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