Semiconductor test circuit for testing a semiconductor...

Details Semiconductor test circuit for testing a semiconductor... Semiconductor test circuit for testing a semiconductor...

2002-04-16

2004-03-09

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189011

Reexamination Certificate

active

06704229

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor test circuit, and more specifically, to a semiconductor test circuit for testing a semiconductor memory device having a write mask function.
2. Description of the Background Art
Conventionally, a system LSI having a logic circuit and an eDRAM (embedded DRAM) merged is being developed. Between the logic circuit and the eDRAM, simultaneous inputting and outputting of several hundred (for instance, 256) data signals is made possible in order to achieve improved data transfer rate. In addition, one write mask signal is provided for every prescribed number (for instance, eight) of data signals, and it becomes possible to inhibit the rewriting of data signals of the corresponding prescribed number of memory cells by controlling the write mask signal. Moreover, in the system LSI, a test circuit is provided for testing with few test pins whether each memory cell within the eDRAM is normal or defective.
FIGS. 17A and 17B
are circuit block diagrams representing the main portion of the test circuit in such a system LSI. For simplicity of the drawings and description, only the portion related to 16 data signals TDQ
0
to TDQ
15
will be described.
In
FIGS. 17A and 17B
, the test circuit includes data scramble registers
80
.
0
to
80
.
15
and EX-OR gates
81
.
0
to
81
.
15
. An external write data signal EDI is input to one input node of each of EX-OR gates
81
.
0
to
81
.
15
. Output signals &phgr;
80
.
0
to &phgr;
80
.
15
from registers
80
.
0
to
80
.
15
are respectively input to the other input nodes of EX-OR gates
81
.
0
to
81
.
15
. Signals &phgr;
80
.
0
to &phgr;
80
.
15
are set, for instance, alternately to the logic high or “H” level and the logic low or “L” level in advance. Output signals from EX-OR gates
81
.
0
to
81
.
15
become internal write data signals TD
0
to TD
15
, respectively.
When external write data signal EDI is set to the “H” level, data signals TD
0
to TD
15
alternately attain the “L” level and the “H” level according to output signals &phgr;
80
.
0
to &phgr;
80
.
15
from data scramble registers
80
.
0
to
80
.
15
. When data signal EDI is set to “L” level, data signals TD
0
to TD
15
alternately attain the “H” level and the “L” level according to output signals &phgr;
80
.
0
to &phgr;
80
.
15
from data scramble registers
80
.
0
to
80
.
15
. Data signals TD
0
to TD
15
are respectively written into 16 memory cells MC
0
to MC
15
designated by an address signal. It is, however, made possible to inhibit writing of data signals TD
0
to TD
7
and/or TD
8
to TD
15
by two write mask signals.
In addition, the test circuit further includes EX-OR gate circuits
82
.
0
to
82
.
15
, determination circuits
83
.
0
to
83
.
15
, and a determination result compressing circuit
84
. An external expected value EEX is input to one input node of each of EX-OR gates
82
.
0
to
82
.
15
. Output signals &phgr;
80
.
0
to &phgr;
80
.
15
from registers
80
.
0
to
80
.
15
are respectively input to the other input nodes of EX-OR gates
82
.
0
to
82
.
15
. EX-OR gates
82
.
0
to
82
.
15
respectively output internal expected values IEX
0
to IEX
15
. External expected value EEX is input in synchronization with read data signals TQ
0
to TQ
15
, and its logic level is set to be the same as the logic level of external write data signal EDI upon writing of write data signals TD
0
to TD
15
corresponding to read data signals TQ
0
to TQ
15
. Thus, internal expected values IEX
0
to IEX
15
respectively become the same as internal write data signals TD
0
to TD
15
.
Determination circuits
83
.
0
to
83
.
15
respectively receive internal expected values IEX
0
to IEX
15
and read data signals TQ
0
to TQ
15
. Determination circuit
83
.
0
determines whether the logic level of read data signal TQ
0
matches the logic level of internal expected value IEX
0
, and causes a signal JG
0
to attain the “L” level that indicates that a corresponding memory cell MC
0
is normal when the logic levels match, and causes signal JG
0
to attain the “H” level that indicates that the corresponding memory cell MC
0
is defective when the logic levels do not match. Other determination circuits
83
.
1
to
83
.
15
are the same as determination circuit
83
.
0
.
Determination result compressing circuit
84
receives output signals JG
0
to JG
15
from determination circuits
83
.
0
to
83
.
15
, and causes a signal Q
0
to attain the “L” level when signals JG
0
to JG
15
are all at the “L” level, and causes signal Q
0
to attain the “H” level when at least one of signals JG
0
to JG
15
is at the “H” level. Thus, the detection of the logic level of signal Q
0
allows the detection of whether 16 memory cells MC
0
to MC
15
are normal or not.
In the case, however, where write mask control is performed with respect to data signals TD
0
to TD
7
, for instance, during a write operation, the data signals of memory cells MC
0
to MC
7
corresponding to data signals TD
0
to TD
7
will not be rewritten so that, even if the logic level of external write data signal EDI during the write operation is made to be the same as the logic level of the expected value EEX during the read operation, internal expected values IEX
0
to IEX
7
and write data signals TD
0
to TD
7
would not necessarily match. Therefore, conventionally, a test that accompanies the write mask control during the write operation did not allow the use of a time reducing technique such as the above-described multi-bit test and thus involved the problem of a longer test time.
SUMMARY OF THE INVENTION
Thus, the principle object of the present invention is to provide a semiconductor test circuit capable of performing a multi-bit test even when a test pattern is written using a write mask function.
A semiconductor test circuit according to the present invention is a circuit for testing a semiconductor memory device having a function simultaneously to perform writing/reading of data signals of a plurality of memory cells designated by an address signal and having a write mask function to inhibit rewriting of the data signals of the plurality of memory cells. The semiconductor test circuit is provided with a write data generating circuit for generating a plurality of internal write data signals to be written into the plurality of memory cells of one unit of write mask according to an external write data signal, an internal expected value generating circuit for generating a plurality of internal expected value signals based on a read data signal from a predetermined memory cell among the plurality of memory cells, and a determination circuit for determining whether the logic levels of a plurality of read data signals from the plurality of memory cells and the logic levels of the plurality of internal expected value signals generated in the internal expected value generating circuit respectively match or not, and outputting a signal of a first level when the logic levels match in all respective pairs, and outputting a signal of a second level when the logic levels do not match at least in one pair. Thus, the plurality of internal expected values are generated based on a read data signal from a predetermined memory cell among the plurality of memory cells, and match/mismatch of the read data signals and the internal expected values is determined per unit of write mask so that the multi-bit test can be performed even when the test pattern is written using the write mask function.
Preferably, the write data generating circuit includes a plurality of registers each of which holds and outputs a data signal supplied in advance, and a plurality of first logical circuits which are respectively provided corresponding to the plurality of registers and each of which generates an exclusive-OR signal of the external write data signal and an output signal of a corresponding register and outputs the generated exclusive-OR signal as the internal write data signal. In this case, a desired test pattern can be written int

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