Semiconductor test apparatus

Details Semiconductor test apparatus Semiconductor test apparatus

2005-04-26

2005-04-26

Assouad, Patrick (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Quality evaluation

C714S764000

Reexamination Certificate

active

06885956

ABSTRACT:
There is disclosed a semiconductor test apparatus enabling writing into an information write space of a block including a failure cell into which block writing is inhibited partially or entirely by the bad block mask function and the fail loop back function. A pattern generation block outputs to an output controller a release signal (S4) for releasing the write inhibit instruction defined by an inhibit signal (S3) and a mask signal (SI). When the output controller receives the release signal (S4), the output controller outputs a write enable signal (WE) to an MUT (4).

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patent: 7-130199 (1995-05-01), None
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