Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2000-07-05
2002-04-30
Wilson, Allan R. (Department: 2815)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C257S797000, C438S401000, C438S975000
Reexamination Certificate
active
06380049
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor substrate and a method of manufacturing a semiconductor device, and particularly to those characterized in an alignment mark for positioning a mask and a method of forming the alignment mark.
2. Description of the Related Art
A process of manufacturing a semiconductor device contains a step of transferring a pattern formed on a mask onto a semiconductor wafer. In this case, as shown in
FIG. 1A
, a predetermined pattern is transferred onto a chip region
2
on a semiconductor wafer
1
to form a layer which comprises the semiconductor device, and at the same time a field alignment mark (X
1
, Y
1
), for example, is transferred onto scribe areas
3
X,
3
Y on the semiconductor wafer
1
. Such an alignment mark comprises plural basic marks M which are regularly arranged as shown in FIG.
1
B. Thereafter, a pattern transfer operation is performed in a next step on the basis of the field alignment mark (X
1
, Y
1
). The alignment marks (X
2
, Y
2
), (X
3
, Y
3
), . . . for use in the respective steps are successively formed while displacing the position. This is because the respective alignment marks are prevented from being overlapped with one another and thus it is avoided that the alignment marks are identifiable.
Followed by the microstructure and multilayer structure of wires of semiconductor devices, a technique of flattening an interlayer insulating film at the lower side of a wiring layer to facilitate the processing of fine wires (microstructure wires) has been increasingly more important. However, the flattening of the interlayer insulating film makes such a disadvantage that it is difficult to see an alignment mark of a substrate for positioning a mask, particularly an alignment mark which is formed by using unevenness of the insulating film. Therefore, the alignment mark is needed to be formed in a step just before the wiring layer is formed, so that the number of alignment marks is increased and an area of the scribe region is also increased.
As a method of solving this problem, Japanese Patent Application Laid-open No. Hei-2-229419 discloses a method (prior art) of forming an alignment mark as shown in FIG.
2
. This method will be hereunder described.
In a first mask step, a first pattern is formed on a chip region of a silicon substrate (wafer), and at the same time an alignment mark
4
a
is formed on a scribe region of the silicon substrate
1
(wafer). In a second mask step, a mask is positioned to the alignment mark
4
a
to form a second pattern on the chip region and at the same time an alignment mark
4
b
is formed.
After the second pattern is formed, a flattening layer
7
and an interlayer insulating film
5
are formed. When a third pattern forming layer
6
formed on the interlayer insulating film
5
is made of an opaque material such as aluminum or the like, an alignment mark
4
c
is formed on the interlayer insulating film
5
on the basis of the alignment mark
4
b
before the opaque film
6
is formed. The alignment mark
4
c
is formed at the same position as the alignment mark
4
a
while overlapped with the alignment mark
4
a.
Before the opaque film
6
is formed, the two alignment marks
4
a
and
4
c
are detected at the same time. However, after the opaque film
6
is formed, the alignment mark
4
a
is unseen, and thus it does not act as an obstacle to position the mask to the alignment mark
4
c
. The alignment marks are formed at the same position in superposition with each other, and this arrangement reduces the occupation area of the alignment marks on the wafer.
According to the technique described in Japanese Patent Application Laid-open No. Hei-2-229419, the alignment mark
4
c
for use when the opaque film
6
is patterned can be formed at the same position as the alignment mark
4
a
. However, in this publication, no description is made on the case where an additional interlayer insulating film is further formed, a contact hole is formed therein and a wiring layer serving as an upper layer is then formed. Further, this publication makes no clear description as to whether the opaque film
6
is left on a scribe region or removed therefrom when the opaque film
6
on the chip region is patterned. When an alignment mark is formed on the scribe region by patterning the opaque film
6
, it is estimated that it is formed at a position where the alignment marks
4
a
,
4
b
,
4
c
are not formed. Accordingly, when a semiconductor device having a multilayered wiring structure is manufactured, the reduction of the occupation area of the alignment marks on the scribe region is not sufficient.
In the above description, a pair of alignment marks are formed in a single step. However, actually, plural alignment marks are formed on the scribe regions
3
X,
3
Y in many cases.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor substrate and a method of manufacturing a semiconductor device which can further reduce the occupation area of the alignment marks.
In order to attain the above object, a semiconductor substrate according to the present invention has a first alignment mark formed on a scribe area, a first interlayer insulating film formed on the first alignment mark, and a second alignment mark comprising an opaque film which selectively covers the first interlayer insulating film and is provided above the first alignment mark, wherein the first alignment mark is shielded by the second alignment mark. The scribe area isolates each chip region from the others.
In this case, the surface of the first interlayer insulating film may be flattened.
Further, a shield film may be formed simultaneously with the opaque film constituting the second alignment mark so as to be away from the second alignment mark at a predetermined distance. Still further, there may be provided a second interlayer insulating film for covering the second alignment mark and a third alignment mark comprising said second interlayer insulating film. The third alignment mark being located on the shield film is formed, for example, by removing the second interlayer insulating film on the shield film. In this case, the surface of the second interlayer insulating film may be flattened.
In the above semiconductor substrate, the first alignment mark comprises plural first basic marks which are arranged regularly, and the second alignment mark comprises plural second basic marks which are arranged regularly and each of which is larger in size than each first basic mark by at least an amount enough for positioning, the first and second basic marks being arranged so that each of the second basic marks is located on each of the first basic marks.
A semiconductor device manufacturing method according to the present invention comprises a step of forming a first alignment mark on a scribe area, forming a first interlayer insulating film, and forming an interlayer alignment mark by patterning the first interlayer insulating film, and a step of depositing and patterning a conductive opaque film to form a second alignment mark shielding the first alignment mark. A semiconductor device is manufactured in a chip region of a semiconductor substrate having the above scribe area for isolating said chip region from the others.
In this case, the method may further comprise a step of flattening the surface of the first interlayer insulating film.
Further, a shielding film which is made of a conductive opaque film may be formed so as to be away from the second alignment mark at a predetermined distance. The method may further comprise a step of forming a second interlayer insulating film so as to cover the second alignment mark, and selectively removing the second interlayer insulating film to form a third alignment mark on the shield film. In this case, the method may contain a step of flattening the surface of the second interlayer insulating film.
In the semiconductor device manufacturing method as described above, the first alignment mark may be
Hamada Masayuki
Hamada Takehiko
Rosenman & Colin LLP
Wilson Allan R.
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