Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Fluid growth from gaseous state combined with subsequent...
Reexamination Certificate
1999-09-03
2002-01-01
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Fluid growth from gaseous state combined with subsequent...
Reexamination Certificate
active
06335269
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor substrate and a method for producing the same and, more particularly to, a non-porous semiconductor layer formed on a porous semiconductor layer and a method for forming the same. Further, the present invention relates to a method of evaluating the shape and state of a surface of a semiconductor substrate, in particular, a porous layer thereof.
The present invention relates also to a semiconductor substrate utilized as a base member for integrated circuits using mainly MOSFETs and bipolar-transistors and a method for forming the same.
2. Related Background Art
Research has been conducted in the integrated-circuit (IC) technologies for silicon-based semiconductor devices to work out a silicon-on-insulator (SOI) structure, in which a monocrystalline silicon film is disposed on an insulator, because the structure reduces parasitic capacitance and facilitates element isolation, thus improving the operation speed of transistor, decreasing the power consumption, improving the integration density, and reducing the total cost.
To form the SOI structure there has been available the Fully Isolation by Porous Silicon (FIPOS) method proposed by Imai in the 1970s through the early 1980s (K. Imai, Solid State Electronics 24 (1981), p. 159). The FIPOS method utilizes the accelerated oxidation phenomenon of porous silicon to form an SOI structure but has a problem that it can inherently form a surface silicon layer only in the shape of islands.
One of the SOI formation technologies attracting the world attention in recent years is the wafer bonding technology, surrounding which have been proposed various methods because the SOI structure provides arbitrariness in the thickness of a surface silicon layer and a buried silicon oxide layer as well as good crystallinity of the surface silicon layer.
Although the bonding method, by which wafers are bonded without an adhesive agent or any other intermediate layers, was proposed originally by Nakamura et al., its research has advanced since 1984, when J. B. Lasky et al. reported the method of thinning one of two bonded wafers and the operation of a MOS transistor formed thereon (J. B. Lasky, S. R. Stiffler, F. R. White, and J. R. Abernathey, Technical Digest of the International Electron Devices Meeting (IEEE, New York, 1985), p. 684).
By the method by Lasky et al., a first wafer which is a monocrystalline silicon wafer incorporated with boron at a high concentration and having formed thereon a low-concentration or n-type epitaxial silicon layer and a second wafer having an oxide film formed on a surface thereof are provided and rinsed, as necessary, and are then brought into close contact with each other, so that the two wafers are bonded to each other by the van der Waals force. The two wafers undergo heat treatment to form covalent bonds therebetween, whereby the bonding strength is enhanced to such a level as not to disturb the production of devices. Then, the first wafer is etched on its back side with a mixture liquid of hydrofluoric acid, nitric acid, and acetic acid, to selectively remove the p
+
silicon wafer so that only the epitaxial silicon layer remains on the second wafer, which is called also the single etch-stop method. However, the ratio of the etch rate for the p
+
silicon to that for the epitaxial silicon (p
−
or n type) is as low as several 10s, thus requiring further improvements to leave a uniform thickness of an epitaxial silicon layer on the entire wafer surface.
Thus, a method has been worked out for conducting selective etching twice. That is, as a first substrate is provided a low-impurity-concentration silicon wafer substrate on a surface of which are stacked a p
++
type Si layer and a low-impurity-concentration layer; then this first wafer is bonded to such a second wafer as described above. Then, the first substrate is thinned by grinding, polishing, or any other mechanical method on its back side. Next, the first substrate undergoes selective etching until the whole surface of the p
++
Si layer buried in the first substrate is exposed. In this case, selective etching due to the difference in the impurity concentration of the substrate is effected by using an alkaline liquid such as ethylene diamine pyrocatechol, KOH, etc. Then, the exposed p
++
Si layer is selectively removed by the selective etching by use of a mixture liquid of hydrofluoric acid, nitric acid, and acetic acid as is the case with the above-mentioned Lasky method, so that only the above-mentioned low-impurity-concentration monocrystalline Si layer is transferred onto the second substrate, which is called the double etch-stop method. This method, by carrying out selective etching a plurality of times, has proved to improve the overall etch selectivity, resulting in a better uniformity in the thickness of the surface Si layer in the SOI.
However, it may be anticipated that the thinning of layers by means of selective etching utilizing the above-mentioned difference in the impurity concentration or composition of the substrate would be affected by the depth profile of the impurity concentration. That is, if the wafers, after the bonding, are heat-treated at a high temperature in order to enhance the bonding strength, the impurity in the buried layer diffuses, so that the etch selectively degrades, resulting in lowering in the uniformity of film thickness. Therefore, the heat treatment after bonding had to be carried out at 800° C. or less. Moreover, because each of the plural times etching would provide a low etch selectivity, the controllability at the time of mass-production was of concern.
In contrast to the above-mentioned method, in which etch selectivity depends on a difference in impurity concentration or composition, Japanese Patent Application Laid-Open No. 5-21338 employs a difference in structure to provide etch selectivity. That is, this method implements an etch selectivity as high as 100,000 due to structural difference between porous silicon with a surface area per unit volume such as 200 m
2
/cm
3
and non-porous silicon, which is called a selective etching method utilizing a structural difference using porous silicon. By this method, a surface of a monocrystalline Si wafer given for a first substrate is anodized to make porous, after which a non-porous monocrystalline silicon layer is epitaxially grown thereon to provide the first substrate. Then, it is bonded to a second substrate and undergoes heat treatment as necessary to enhance the bonding strength. Subsequently grinding, polishing or the like is carried out to remove the back side of the first substrate, thus exposing the porous silicon layer in its entirety. Next, the porous silicon is selectively removed by etching to, with the result that the above-mentioned non-porous monocrystalline silicon layer is transferred onto the second substrate. Since a high etch selectivity as much as 100,000 was obtained, the uniformity in the thickness of the SOI layers obtained was impaired little by the etching, reflecting the uniformity of the monocrystalline silicon layer during the epitaxial growth as such. That is, as is the case with a commercially available CVD epitaxial growth apparatus, this method attains an in-wafer uniformity, for example 1.5% to 3% or less, for the SOI-Si layer. This method uses, as the material for selective etching, the porous silicon which is used as the material for selective oxidation in the FIPOS method. Therefore, this method does not limit the porosity to about 56% but prefers a rather low value of about 20%. Note here that the method for producing SOI structures disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-21338 was named ELTRAN (trademark) in a report by Yonehara et al. (T. Yonehara, K. Sakaguchi, N. Sato, Appl. Phys. Lett. 64 (1994), p. 2108).
Also, since porous silicon will not become the structural member of a final product, the structural change and the coarsen
Bowers Charles
Canon Kabushiki Kaisha
Christianson Keith
Fitzpatrick ,Cella, Harper & Scinto
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