Active solid-state devices (e.g. – transistors – solid-state diode – Including region containing crystal damage
Reexamination Certificate
1998-04-29
2001-04-24
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Including region containing crystal damage
C257S611000, C257S913000
Reexamination Certificate
active
06222252
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor substrate and a process for producing the same. More particularly, the present invention relates to a semiconductor substrate for use in memory devices and logic devices having an MOS structure, an MOS semiconductor device, and a process for producing the same.
A CZ (Czochralski) silicon substrate taken off from a single crystal silicon grown by the Czochralski method (CZ method) has hitherto been mainly used as a silicon wafer which serves as a substrate for a semiconductor device. Further, an epitaxial wafer prepared by forming a single crystal silicon layer on a CZ silicon substrate by vapor phase epitaxy has also been used as the semiconductor substrate.
When a device having an MOS structure is prepared using the silicon substrate, oxygen contained in the semiconductor substrate is precipitated by heat treatment in the course of the production process, forming precipitation of oxygen, i.e., bulk micro defects (BMD). These bulk micro defects formed in the semiconductor substrate can incorporate therein metal impurities. Therefore, the effect of eliminating electrical failure and the like attributable to metal impurities in the course of device formation, that is, IG (intrinsic gettering) effect (hereinafter often referred to as “gettering effect”), can be expected. Basically, the higher the density of bulk micro defects, the better the IG effect. In order to efficiently attain the IG effect, it is generally considered that the density of bulk micro defects should be not less than 10
8
defects/cm
3
.
Formation of bulk micro defects in the semiconductor substrate, however, is disadvantageous in that presence of bulk micro defects in a device forming zone is causative of electrical failure, such as poor gate silicon oxide proof voltage or junction leak failure. For this reason, a DZIG wafer, wherein the device forming zone has been brought to a denuded zone (DZ), is generally used. In this DZIG wafer, bulk micro defects are formed at a density of 10
8
to 10
10
defects/cm
3
in the interior of the semiconductor substrate. This bulk micro defect density of DZIG is convenient for attaining the IG effect.
When a device having an MOS structure is formed using a DZIG substrate having a bulk micro defect density of 10
8
to 10
10
defects/cm
3
, however, slipping or dislocation is created in forming zone, resulting in deteriorated mechanical strength of the semiconductor substrate. That is, when the bulk micro defect density of the semiconductor substrate is high, the mechanical strength of the semiconductor substrate is lowered. In this case, for the semiconductor substrate alone, the lowering in mechanical strength can be reduced by controlling the mechanical strength through heat treatment in a temperature region (900° C. or above) where bulk micro defects are grown. On the other hand, when a device is formed on the semiconductor substrate, final heat treatment conditions are automatically determined by the device forming process, making it practically difficult to control the mechanical strength by heat treatment at 900° C. or above.
Thus, the IG effect and the high mechanical strength are contradictory properties, and, at the present time, it is difficult to provide a semiconductor substrate which has a good balance between these properties.
DISCLOSURE OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor substrate that can satisfy both IG effect and high mechanical strength requirements, which could not have simultaneously satisfied, that is, a semiconductor substrate that can efficiently exhibit the IG effect by virtue of the creation of bulk micro defects in the interior of the semiconductor device and, at the same time, is less likely to create slipping or dislocation and has excellent mechanical strength.
The present inventors have unexpectedly found that an enhancement in bulk micro defect density in terms of the number of bulk micro defects in the semiconductor substrate to a given level, which has not been found in the prior art, can significantly reduce slipping and dislocation, can enhance the mechanical strength to a satisfactory level and in addition can develop satisfactory IG effect, which has been led to the completion of the present invention.
The semiconductor substrate of the present invention which has been made based on the above finding has bulk micro defects dispersed at a density of not less than 10
11
micro defects/cm
3
in the interior thereof.
According to a preferred embodiment of the present invention, the initial concentration of oxygen in the semiconductor substrate is not more than 9×10
17
atoms/cm
3
in terms of conversion factor IOC(international oxygen coefficient)-88, the average size of bulk micro defects present in the interior of the semiconductor substrate is not more than 300 nm, the semiconductor substrate has a resistivity of not more than 0.05 &OHgr;·cm, the concentration of boron in the semiconductor substrate is 10
18
to 10
20
atoms/cm
3
, and the semiconductor substrate has a maximum breaking shear stress of not less than 14 MPa as measured by a flexural test at a displacement speed of 0.1 mm/min according to the procedure as set forth in JIS R 1601.
According to another preferred embodiment of the present invention, the semiconductor substrate has thereon a denuded zone formed by either epitaxial growth or high-temperature annealing in a reducing atmosphere, an inert gas atmosphere, or an atmosphere of a mixed gas composed of a reducing gas and an inert gas.
According to another aspect of the present invention, there is provided an MOS type semiconductor device comprising: the above semiconductor substrate; and at least an MOS transistor or capacitor provided on the semiconductor substrate.
According to a further aspect of the present invention, there is provided a process for producing the above semiconductor substrate, comprising the steps of: heat-treating a semiconductor substrate at 450 to 800° C. for one hr or longer for nucleation; and then heat-treating the semiconductor substrate at 900 to 1100° C. for growth. According to a preferred embodiment of the present invention, a denuded zone is formed on the surface of the above semiconductor substrate by either epitaxial growth or high-temperature annealing in a reducing atmosphere, an inert gas atmosphere, or an atmosphere of a mixed gas composed of a reducing gas and an inert gas.
REFERENCES:
patent: 5994761 (1999-11-01), Falster et al.
Wolf, Stanley, et al., Silicon Processing for the VLSE Era, Lattice Press, pp. 54 and 59-70, 1986.
Miyashita Moriya
Numano Masanori
Crane Sara
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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