Semiconductor structures and methods for manufacturing such stru

Details Semiconductor structures and methods for manufacturing such stru Semiconductor structures and methods for manufacturing such stru

1978-05-08

1979-05-22

Rutledge, L. Dewayne

Metal treatment

Barrier layer stock material, p-n type

With recess, void, dislocation, grain boundaries or channel...

148175, 156647, 357 50, H01L 21302, H01L 2120, H01L 2712

Patent

active

041557832

ABSTRACT:
Semiconductor integrated circuit structures and manufacturing methods wherein isolation grooves are etched into a semiconductor body by first bringing an anisotropic etchant in contact with portions of the surface of the body which are exposed by windows formed in an etch-resistant mask to form grooves with side walls which intersect the surface at acute angles. Next, an isotropic etchant is brought in contact with the walls of the etched grooves to remove portions of the body which are underneath the etch-resistant mask such that the mask extends over the side walls of the resulting grooves, the bottom walls of such grooves are disposed under the windows and the side walls maintain acute angle intersection with the surface. Junction isolation regions are formed by ion implanting particles into the bottom walls of the grooves, the maks shielding the side walls from such particles. This self-aligning process accurately controls the placement of the junction isolation regions and thereby reduces the depth required for the grooves in providing dielectric isolation. Because the grooves have side walls which intersect the surface at acute angles, and because the grooves are relatively shallow because of the addition of accurately placed junction isolation regions, subsequent metallization processing is more readily controllable.

REFERENCES:
patent: 3716425 (1973-02-01), Davidsonn
patent: 3901737 (1975-08-01), Dash
patent: 3920482 (1975-11-01), Russell
patent: 3966514 (1976-06-01), Feng et al.
patent: 3986200 (1976-10-01), Allison
patent: 4047195 (1977-09-01), Allison
patent: 4047975 (1977-09-01), Widmann
patent: 4056413 (1977-11-01), Yoshimura
patent: 4066473 (1978-01-01), O'Brien
Aboaf et al., "Dielectric Isolation" IBM-TDB, 18 (1976) 3295.

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