Semiconductor structure with multiple fins having different...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S347000, C257S365000, C257S302000, C257SE25011

Reexamination Certificate

active

07544994

ABSTRACT:
Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.

REFERENCES:
patent: 6214681 (2001-04-01), Yu
patent: 6413802 (2002-07-01), Hu et al.
patent: 6909147 (2005-06-01), Aller et al.
patent: 2004/0222477 (2004-11-01), Aller et al.
patent: 2004/0266076 (2004-12-01), Doris et al.
patent: 2005/0215014 (2005-09-01), Ahn et al.
A. Breed, et al. “Dual-gate (FinFET) and Tri-Gate MOSFETs: Simulation and Design”—Semiconductor Device Research Symposium, Dec. 2003, pp. 150-151.

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