Semiconductor structure using local planarization with self-alig

Details Semiconductor structure using local planarization with self-alig Semiconductor structure using local planarization with self-alig

1994-08-22

1995-12-19

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257382, 257383, 257384, 257385, 257635, 257644, 257754, 257773, H01L 2348

Patent

active

054770742

ABSTRACT:
A CMOS integrated circuit uses self-aligned transistors combined with local planarization in the vicinity of the transistors so as allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer and underlying oxide layer are removed only in the area of the buried contact, while an overlying metal or polysilicon conductive layer contacts the upper surface of certain of the transistor gate structures, the topside insulating layer of which has been removed for this purpose.

REFERENCES:
patent: 5166771 (1992-11-01), Godhino et al.
patent: 5182225 (1993-01-01), Matthews
patent: 5200358 (1993-04-01), Bollinger et al.

Affiliated with

Also associated with

Rating

Semiconductor structure using local planarization with self-alig does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor structure using local planarization with self-alig, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor structure using local planarization with self-alig will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-993652