Semiconductor structure having interconnects on a projecting...

Details Semiconductor structure having interconnects on a projecting... Semiconductor structure having interconnects on a projecting...

1999-06-24

2001-08-14

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000

Reexamination Certificate

active

06274897

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to methods for forming a semiconductor structure, and more specifically, to a method for forming a semiconductor structure having a trench with a reduced aspect ratio, a reduced retrograde, or both.
BACKGROUND OF THE INVENTION
In order to fit more circuitry on a semiconductor wafer, semiconductor process engineers are steadily reducing the dimensions of the elements that compose integrated circuits and of the spaces and trenches that separate these elements. These integrated elements may include, for example, transistors and conductive coupling interconnects, such as conductive paths or lines. Such a decrease in the trench dimensions, particularly the trench width, often causes a number of problems. For example, the decrease in trench width may increase the difficulty of filling a trench with a material or of removing the material from the trench. As discussed below in conjunction with
FIG. 1
, residue or stringers of conductive material that are not removed from a trench may cause short circuits between circuit elements. Such problems and conventional solutions thereto are discussed in U.S. Pat. No. 5,302,233, which is entitled “Method for Shaping Features of a Semiconductor Structure Using Chemical Mechanical Planarization (CMP),” issued on Apr. 12, 1994, and is incorporated by reference herein.
FIG. 1
is a cut away top view of a portion
10
of a semiconductor device, such as a dynamic random access memory (DRAM), having reduced element and trench dimensions. Portion
10
includes three word interconnects or lines
12
a-c
, which are formed on a substrate
13
and carry signals that fire respective rows of memory cells (not shown) when an external device, such as a processor (not shown), addresses these rows. A field oxide region
14
isolates active substrate areas
16
a-b
from one another. The word lines
12
are often etched from one or more layers that are formed on the substrate
13
and the field regions
14
. Such etching forms trenches
20
between adjacent word lines
12
. As shown, the trenches
20
are narrowest where the word lines
12
cross over the field oxide
14
. Typically, storage-cell transistors (not shown) are formed in the active areas
16
. Plates
18
a-b
of data storage capacitors associated with active areas
16
a-b
respectively are formed from a layer of conductive material, such as polysilicon, that is deposited over the word lines
12
, field region
14
, and active areas
16
.
Because the aspect ratios (ie., depth or height to width ratio) for the trenches
20
are of ten relatively large, and because the cross-sectional profiles of the trenches
20
are often retrograde, it is often difficult to remove material that has been deposited within the trenches
20
. A retrograde, i.e., “bottle neck”, cross-sectional profile occurs when the width of the opening to the trench
20
is smaller than the width of the trench
20
beneath the opening. The residue of the conductive material within a trench
20
may form a short circuit, i.e., stringer
22
, between two or more capacitor plates
18
, and render defective each of the memory cells associated with a respective one of the shorted plates
18
. For example, the stringer
22
, if present, may render defective both of the memory cells associated with capacitor plates
18
a
and
18
b
, respectively.
One technique for removing the conductive material from the trenches
20
, and thus reducing or eliminating the formation of the stringers
22
, is overetching the layer of conductive material during the formation of plates
18
. Such overetching, however, typically reduces the area of plates
18
, and thus reduces the storage capacity of the storage capacitors.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method is provided for forming a semiconductor structure. A region is formed in a substrate, and projects out of the substrate surface. First and second interconnects each having a predetermined thickness and a surface approximately parallel to the substrate surface are formed on the region. The first and second interconnects define a trench therebetween. A third interconnect is formed on the substrate. The thicknesses of the first and second interconnects are reduced a first amount and the thickness of the third interconnect is reduced a second amount. In a related aspect of the invention, the second amount is less than the first amount.
In accordance with another aspect of the invention, the thicknesses of the first and second interconnects are reduced by polishing the approximately parallel surfaces.
In accordance with yet another aspect of the invention, the thicknesses of the first and second interconnects are reduced by polishing the approximately parallel surfaces, and the mouth of the trench is widened by polishing the edges between each of the approximately parallel surfaces and the sides of the respective first and second interconnects that face the trench.
In accordance with still another aspect of the invention, a layer of material is formed on the substrate and the region. The layer is planarized, and the first, second, and third strips are formed from the planarized layer.
An advantage provided by one aspect of the invention is a reduction in the aspect ratios of trenches between adjacent integrated elements.
An advantage provided by another aspect of the invention is an improvement in the cross-section profile of the trenches between adjacent elements.
An advantage provided by still another aspect of the invention is making the surfaces of the interconnects perfectly or nearly perfectly planar. Such planarity allows the use or increases the effectiveness of subsequent etch and CMP processes that are designed to end at the interconnect surfaces or in layers or materials on the interconnect surfaces.
An advantage provided by yet another aspect of the invention is a planarized surface that provides a wider process margin for photolithography.


REFERENCES:
patent: 4824521 (1989-04-01), Kulkarni et al.
patent: 5055158 (1991-10-01), Gallagher et al.
patent: 5140389 (1992-08-01), Kimura et al.
patent: 5270241 (1993-12-01), Dennison et al.
patent: 5302233 (1994-04-01), Kim et al.
patent: 5346587 (1994-09-01), Doan et al.
patent: 5411909 (1995-05-01), Manning et al.
patent: 5529946 (1996-06-01), Hong
patent: 5685947 (1997-11-01), Tseng et al.
patent: 5804851 (1998-09-01), Noguchi et al.
patent: 6-151764 (1994-05-01), None

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