Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1999-05-10
2001-01-16
Ng{circumflex over (o)}, Ng{circumflex over (a)}n V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S773000, C257S774000
Reexamination Certificate
active
06175125
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the manufacture of semiconductor devices, and more specifically it relates to a chip in which a large number of vias can be formed and then tested accurately.
BACKGROUND
A semiconductor chip is commonly formed as a multi-level structure that includes a layer of a vias, conductors that interconnect circuit nodes in the layers above and below the via layer. The layer above a via layer is a conductive film that is shaped to interconnect vias or to connect vias to other circuit nodes. The structure below the via layer may be a similar conductive film or it can be a surface of the substrate that has for example transistor terminals. A dielectric supports the vias and insulates the circuit nodes.
THE PRIOR ART
It is a general object in this art to test and improve the manufacturing steps that form these vias. In one technique of the prior art, a wafer or a chip or a few chips on a wafer are formed with a layer having a large number of vias. The conductive layers above and below the via layer are shaped to interconnect the vias into a series string that can be tested by testing the continuity of the string.
A string of vias will produce a resistance that is the sum of the individual resistances. A defective via has an open circuit resistance, and a string with one defective via has an open circuit resistance. A string of good vias has a resistance equal to the product of the number of vias in the string and the resistance of one via—a few ohms.
In a test using this prior art method, a chip is manufactured with a string of vias that have been formed by a process that is being tested. Probes are connected to the ends of the via string and the resistance is measured. The test gives an improved understanding of the associated manufacturing process that may lead to improvements in the process.
It would be advantageous to test a very large number of vias in a test wafer. In the specific example that will be described later, the test structure has 58,982,400 vias. Such a string has a resistance of about 590 megohms. (A good via has a resistance of a few ohms, about 9 or 10 ohms in the technology used for the preferred embodiment.) It is not feasible to measure a resistance this high in a semiconductor device, and the string has an effectively open circuit resistance, and it is not possible to distinguish such a string of good vias from a similar string with a defective via.
SUMMARY OF THE INVENTION
I form a large number of vias into separate strings that each have a resistance that is easily measured. The specific embodiment that will be described later has a total of 58,982,400 vias (as in the example of the prior art) and these vias are organized in an array of 900 rows and 36,536 columns. (The row and column terminology is of course arbitrary.) The 900 vias in each column are interconnected into series strings. Thus a string of good vias has a resistance of about 8100 ohms (9 ohms/via×900 vias). This resistance value is easily measured and readily distinguished from the open circuit resistance of an otherwise similar string with a defective via.
I provide a multiplexor circuit on the test structure to connect the strings one at a time in to a circuit that tests for continuity. The multiplexor addresses the via strings one at a time in response to a sequence of address signals that are supplied to the test structure from a computer. Thus the test is easily controlled and the identification of a defective via string is available at the computer.
Other features of the invention will appear in the description of a preferred embodiment.
REFERENCES:
patent: 4956611 (1990-09-01), Maltiel
patent: 5514974 (1996-05-01), Bouldin
patent: 5699282 (1997-12-01), Allen et al.
patent: 5736863 (1998-04-01), Liu
patent: 5900645 (1999-05-01), Yamada
patent: 5982042 (1999-11-01), Nakamura
Ackerman Stephen B.
Ng{circumflex over (o)} Ng{circumflex over (a)}n V.
Robertson William S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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