Semiconductor structure for recessed isolation oxide

Details Semiconductor structure for recessed isolation oxide Semiconductor structure for recessed isolation oxide

1981-01-29

1984-07-31

Ozaki, G.

Metal treatment

Barrier layer stock material, p-n type

With recess, void, dislocation, grain boundaries or channel...

29576W, 148 333, 148187, H01L 2131

Patent

active

044628463

ABSTRACT:
A method of providing recessed oxide isolation layers employs prior art techniques to the point at which a photoetched recess has exposed the semiconductor surface in which the recessed oxide isolation layer is to be grown. The semiconductor wafer is then subjected to a nitride layer formation procedure. The nitride layer formed extends into a photoetched recess and forms a nitride layer on the side surfaces of the recess. The newly deposited nitride layer is subjected to an etching process which etches vertically only, exposing the semiconductor surface in a pattern defined by the nitride coated recess. Since the recess walls are lined with a nitride layer, subsequent oxidation growth is restricted to the recess defined by the nitride coated walls. There is no intrusion of the recessed oxide isolation layer into adjacent active areas of the semiconductor material. Thus, the full active width of adjacent areas of the semiconductor is preserved and greater utilization of the available surface area achieved.

REFERENCES:
patent: 3761327 (1973-09-01), Harlow et al.
patent: 4001465 (1977-01-01), Graul et al.
patent: 4002511 (1977-01-01), Magdo et al.
patent: 4234362 (1980-11-01), Riseman
patent: 4261763 (1981-04-01), Kumar et al.
patent: 4272308 (1981-06-01), Varshney

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