Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-09-12
2006-09-12
Tran, Thien F. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S353000, C257S354000
Reexamination Certificate
active
07105897
ABSTRACT:
This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.
REFERENCES:
patent: 6635543 (2003-10-01), Furukawa et al.
patent: 2005/0045951 (2005-03-01), Yamada et al.
Fenouillet-Beranger, C. et al., “Requirements for ultra-thin film devices and new materials on CMOS Roadmap”, 2003 IEEE O-7803-7815 pp. 145-146, ST Microelectronics, Grenoble, France.
Fukuda, Y. et al., “Special Edition on 21st Century Solutions: SOI-CMOS Device Technology”, OKI Technical Review 185, vol. 68 (2001) pp. 54-57.
Koh, R., “Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μ m SOI-MOSFET”, Jpn. J. Appl. Phys., vol. 38 (1999) pp. 2294-2299.
Roche, P., et al., “Comparisons of Soft Error Rate for SRAMs in Commercial SOI and Bulk Below the 130-nm Technology Node”, IEEE Transactions on Nuclear Science, vol. 50, No. 6 (2003) pp. 2046-2054.
Fenouillet-Beranger, C. et al., “Requirements for ultra-thin film devices and new materials on CMOS Roadmap”, 2003 IEEE O-7803-7815 pp. 145-146.
Mandelman, J.A. et al., “Floating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)”, Proceedings 1996 IEEE International SOI Conference, Oct. 1996 IEEE 0-7803-3315-2 pp. 136-137.
Yang, M., “High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations”, 2003 IEEE IEDM 0-7803-7872 pp. 453-456.
Rim, K., et al., “Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs”, 2003 IEEE IEDM 0-7803-7872 p. 4952.
Chen Hao-Yu
Chen Hung-Wei
Wang Chao-Hsiung
Wu Ping-Kun
Yang Fu-Liang
Duane Morris LLP
Taiwan Semiconductor Manufacturing Company
Tran Thien F.
LandOfFree
Semiconductor structure and method for integrating SOI... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor structure and method for integrating SOI..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor structure and method for integrating SOI... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3561607