Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
1999-10-12
2001-01-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S189090, C365S200000
Reexamination Certificate
active
06181625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device, and more particularly to a reference voltage generation circuit which generates the word line voltage of a semiconductor storage device which stores multiple-bit data in one memory cell.
2. Description of the Prior Art
Recently, in response to the request for a large-capacity semiconductor storage device, a semiconductor storage device which stores multiple-bit data in one cell with the use of the multiple-value technology has received much attention. The multiple-value technology will be described with a mask ROM as an example.
A mask ROM using the multiple-value technology must store multiple-bit (for example, two-bit or four-bit) data in one memory cell transistor. To do so, the threshold voltage of each memory cell transistor must be set to one of four or more threshold voltages according to the data to be stored. For example, to store two-bit data in one memory cell transistor, the threshold voltage must be set to one of 2
2
=4 types of threshold voltages according to the data to be stored; to store four-bit data in one memory cell transistor, the threshold voltage must be set to one of 2
4
=16 types of threshold voltages according to the data to be stored. The threshold is set up by the ion implantation technology during manufacturing.
Data is read from a memory cell transistor, which stores multiple-but data, as described below.
For a mask ROM which does not use the multiple-value technology, that is, a mask ROM which stores one-bit data in one memory cell transistor, one voltage level need be applied to a word line. This is because, in order to store one-bit data in one memory cell transistor, one of two threshold voltage levels need be set up for data to be stored. This means that applying the intermediate of the two threshold voltage levels to the word line indicates which threshold voltage level the memory cell transistor has. In this case, the memory cell transistor having one of two threshold values is set to ON, and the memory cell transistor having the other threshold value is set to OFF. Therefore, data may be read from the selected memory cell.
However, for a mask ROM using the multiple-value technology, each memory cell transistor has four or more threshold voltage levels. Therefore, to check the threshold voltage each memory cell transistor has, it is necessary to apply multiple levels of voltage to the word line one after another. For example, when one memory cell transistor contains two-bit data, that is, when the memory cell transistor has four threshold voltage levels, Vt
0
, Vt
1
, Vt
2
, and Vt
3
, it is necessary to apply the intermediate voltage (T
1
V) of Vt
0
and Vt
1
, the intermediate voltage (T
2
V) of Vt
1
and Vt
2
, and the intermediate voltage (T
3
V) of Vt
2
and Vt
3
, one after another, to the word line to check which threshold voltage level the memory cell transistor has. This means that a mask ROM storing two-bit data in one memory cell transistor requires a circuit which generates three levels of word line voltage.
Similarly, when one memory cell transistor contains four-bit data, the mask ROM requires a reference voltage generation circuit which generates 15 (16−1) levels of word line voltage.
Although many circuits which generate these reference voltages have been introduced, the threshold voltage of a memory cell transistor is not always a desired threshold voltage because of manufacturing process problems. This means that the relation between the reference voltage and the memory cell transistor threshold voltage is not always a desired relation because of manufacturing problems.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention to provide a semiconductor storage device capable of making the relation between the reference voltage and the memory cell transistor threshold voltage a desired relation.
The present invention provided a semiconductor storage device which supplies voltage developed at an output end to word lines, the semiconductor storage device comprising resistor means connected between a first power source end and the output end; and first and second dummy cell transistors connected in series between a second power source end and the output end, wherein the first dummy cell transistors and the second dummy cell transistors are manufactured in the same manufacturing process. Preferably, the gates of the first and second dummy cell transistors are connected to the output end. In addition, the threshold voltage of the first dummy cell transistors and the threshold voltage of the second dummy cell transistors are preferably different.
The present invention also provides a semiconductor storage device comprising a memory cell array composed of a plurality of memory cell transistors; a plurality of word lines each of which selects one of the plurality of memory cell transistors; an X decoder which activates a predetermined word line out of the plurality of word lines in response to an address signal; and means for supplying a reference voltage to the predetermined word line that is activated, wherein the means for supplying the reference voltage comprises resistor means connected between a first power source end and an output end; first and second dummy cell transistors connected in series between a second power source end and the output end; and means for supplying the voltage developed at the output end to the predetermined word line that is activated, wherein the first dummy cell transistors and the second dummy cell transistors are manufactured in the same manufacturing process. Preferably, each of the memory cell transistors stores therein data, composed at least two bits, with a threshold voltage thereof, wherein the threshold voltage of the first dummy cell transistors is substantially equal to the threshold voltage corresponding to predetermined data stored in the memory cell transistors, and wherein the threshold voltage of the second dummy cell transistors is substantially equal to the threshold voltage of data different from the predetermined data.
The present invention also provide a semiconductor storage device, wherein ion implantation is done during a manufacturing process for the memory cell transistors to set up a plurality of threshold values exceeding a range of a power source voltage.
REFERENCES:
patent: 4653023 (1987-03-01), Suzuki et al.
patent: 4802138 (1989-01-01), Shimamune
patent: 5025417 (1991-06-01), Miyamoto et al.
patent: 5936888 (1999-08-01), Sugawara
patent: 5963484 (1999-10-01), Jung
Le Thong
NEC Corporation
Nelms David
Young & Thompson
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