Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-11-03
2001-04-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C365S230060, C365S233100
Reexamination Certificate
active
06219285
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a technique of increasing the operating speed of a semiconductor storage device, and more particularly relates to controlling column selection and data line potential amplification in a DRAM.
FIG. 11
schematically illustrates an ordinary configuration of a conventional DRAM. In the DRAM shown in
FIG. 11
, an address signal is input to an input/output (I/O) interface and controller
50
. A row address represented by the address signal is decoded by a row decoder
51
to select a particular word line WL. The data of a plurality of memory cells M belonging to the selected word line WL are output to associated bit lines BL. Then, the data read out on the bit lines BL are amplified by a sense amplifier SA. Thereafter, a column address AY is provided to the I/O interface
50
and then decoded by a column decoder
52
to select a particular column select line CSL. When the particular column select line CSL is selected, a column switch CS connected to the column select line CSL turns ON. As a result, the data on an associated bit line BL, which is connected to the column switch CS, is read out on an associated data line DL. The data read out on the data line DL is further amplified by a read amplifier (not shown in FIG.
11
), selected by an I/O controller
53
and then output through the I/O interface
50
to an external component. Although not specifically shown in
FIG. 11
, the bit lines BL and data lines DL are each made up of a pair of complementary bit lines and a pair of complementary word lines, respectively.
The DRAM shown in
FIG. 11
further includes a plurality of redundant memory cells RM to back up and substitute for memory cells with faults that are brought about during a manufacturing process. To replace a faulty memory cell M with an associated redundant memory cell RM, a redundant column decoder
52
, which is integrated with the column decoder
52
, selects a particular redundant column select line RCSL. When a redundant column switch RCS, which is connected to the redundant column select line RCSL, turns ON, the data on an associated redundant bit line RBL is read out onto the data line DL.
Although not shown in
FIG. 11
, the I/O interface and controller
50
generates various types of control signals such as address latch signal, sense amplifier starting signal, read amplifier starting signal and data output timing signal and controls data readout operations using these control signals.
FIG. 9
is a block diagram illustrating a column-selecting circuit section of the DRAM shown in FIG.
11
.
FIG. 10
is a timing diagram of respective control signals used in this circuit section. As shown in
FIG. 9
, a column pre-decoder
901
pre-decodes a column address AY to generate a column address pre-decoded signal YP, which is in turn decoded by a column decoder
902
to generate a column select signal Y. Then, the column select signal Y is input to an associated column switch CS, thereby selecting a normal column.
The column address AY and a redundant column address RAY, which is the column address of a faulty memory cell to be replaced with a redundant memory cell, are input to a column redundancy decision circuit
903
. Responsive to a redundancy clock signal RCLK, the decision circuit
903
compares the column address AY to the redundant column address RAY to see if these addresses match up to each other. If the given column address AY is identical to the redundant column address RAY, then the decision circuit
903
outputs a redundant column address pre-decoded signal SYP to a redundant column decoder
904
, which decodes the signal SYP to output a redundant column select signal SY. Responsive to the signal SY, the column switch CS selects an associated redundant column.
A pre-decoder controller
905
is provided to disable the selection of a normal column when the redundant column is selected. On receiving the signal SYP from the decision circuit
903
, the controller
905
decides that a redundant column is now being selected. Then, the controller
905
outputs an assert
egate signal NEN such that the normal column address pre-decoded signal YP output from the column pre-decoder
901
is negated. As a result, the normal column select signal Y output from the column decoder
902
is also negated.
In
FIG. 9
, an address transition detector (ATD)
906
generates a one-shot pulse every time a signal representing the column address AY rises or falls. A delay circuit
907
delays the one-shot pulse generated by the ATD
906
to produce data line pre-charging and amplifying signals DLPRE and DLSEN such as those shown in
FIG. 10
, and output these signals to a read amplifier
908
, thereby pre-charging and amplifying the data line DL.
However, it takes a rather long time for the conventional DRAM to select a column due to its configuration. This drawback will be detailed below.
In
FIG. 9
, the column pre-decoder
901
is not allowed to output the normal column address pre-decoded signal YP until the decoder
901
receives the assert
egate signal NEN from the pre-decoder controller
905
. Accordingly, a phase difference &thgr; exists between a time the normal column select signal Y is output to select a normal column and a time the redundant column select signal SY is output to select a redundant column as shown in FIG.
10
. Due to the existence of the phase difference, the following control should be performed.
The data line DL should be pre-charged before the data on the bit line BL is read out on the data line DL as a result of column selection. That is to say, it is only after the data line DL has been pre-charged that the data on the bit line may be read out on the bit line and the potential on the line be amplified. However, since there is the phase difference, the interval between a reference time and a point in time the data on the bit line is read out on the data line differs depending on whether a normal or redundant column is selected. Accordingly, the start point of data line potential amplification should be no earlier than a point in time the later column select signal is output. As a result, the start of data readout operation is delayed. On the other hand, the endpoint of data line pre-charging should be coincident with a point in time the earlier column select signal is output. Thus, a long time margin, including the phase difference &thgr;, is needed after data line pre-charging is finished and before data line potential amplification is started. This delay constitutes an obstacle to speeding up the readout operation of the storage device.
Also, the data line pre-charging and amplifying signals DLPRE and DLSEN supplied to the read amplifier
908
are generated by getting the one-shot pulses, which are output from the ATD
906
every time the column address signal AY rises or falls, delayed by the delay circuit
907
. Accordingly, there should be a long time interval after the column address signal AY rises or falls and before the signal DLPRE or DLSEN is generated. Furthermore, the characteristics of delay devices included in the delay circuit
907
are variable due to a variation in voltage or process-induced errors. Thus, if a long delay should be defined for these delay devices, then the delay times defined are greatly variable. As a result, if the data line pre-charging and amplifying signals DLPRE and DLSEN should be generated taking this variation into account, the long operation margin is needed as shown in
FIG. 10
, thus interfering with the high-speed operation of the storage device.
SUMMARY OF THE INVENTION
An object of the present invention is speeding up the operation of a semiconductor storage device by eliminating a phase difference between normal and redundant column select signals and thereby shortening the interval after a data line has been pre-charged and before a data line potential starts to be amplified.
Another object of the present invention is generating data line pre-charging and amplifying signals with a reduced operation margin in the semiconducto
Murakuki Yasuo
Shibayama Akinori
Harness & Dickey & Pierce P.L.C.
Mitsushita Electric Industrial Co., Ltd.
Nelms David
Yoha Connie C.
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