Semiconductor storage device with redundancy arrangement

Details Semiconductor storage device with redundancy arrangement Semiconductor storage device with redundancy arrangement

1990-09-20

1991-09-10

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 36523008, 371 103, G11C 700, G11C 11413

Patent

active

050479830

ABSTRACT:
In a semiconductor storage device having a spare memory, an input address signal is checked by an address comparator circuit. When the input address signal indicates an address which is to be relieved, the spare memory is selected instead of a memory array on the basis of the output of the address comparator circuit at that time. In conventional system, the access time of the semiconductor memory is restricted substantially by the operating time of the address comparator circuit during this operation. Accordingly, for enabling a quick access of the semiconductor memory, an address signal to be supplied to the address comparator circuit is output from a proceeding stage circuit of a plurality of amplification stages which form an address buffer circuit.

REFERENCES:
patent: 4104735 (1978-08-01), Hoffmann et al.
patent: 4247921 (1981-01-01), Itoh et al.
patent: 4532607 (1985-07-01), Uchida
patent: 4538245 (1985-08-01), Smarandoiu et al.
IBM-TDB, vol. 19, No. 1, Jun. 1976, by Huffman et al. "Memory Address Decode Circiuit", pp. 28-29.

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