Semiconductor storage device with macro-cell with monitoring of

Details Semiconductor storage device with macro-cell with monitoring of Semiconductor storage device with macro-cell with monitoring of

1995-12-27

1997-12-23

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518904, 36518911, G11C 1300

Patent

active

057012679

ABSTRACT:
It is an object of the present invention to realize bypass of input data in a macro-cell such as a FIFO memory etc. to facilitate test and evaluation about other macro-cells. A bypass route (6) is provided between an input port (DI) and an output port (DO) in a FIFO memory (1) and a data bypassing selector (8) is further provided for selecting the bypass route (6) and a sense amplifier (7) of a read bit line (R.BL). Then, in the test mode, a first selector control signal (S) is set to an L level and a second selector control signal (S) of opposite phase is set to an H level. Thus, in the test mode, a data inputted from the input port (DI) is outputted from the output port (DO) by way of the bypass route (6) without via memory cells (MC1-MCX).

REFERENCES:
patent: 5040150 (1991-08-01), Naitoh et al.
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5255239 (1993-10-01), Taborn et al.
patent: 5502677 (1996-03-01), Takahashi
patent: 5502683 (1996-03-01), Marchioro
patent: 5541886 (1996-07-01), Hasbun
IEEE 1992 Custom Integrated Circuits Conference, pp. 7.4.1-7.4.4, 1992, Masatoshi Kimura, et al., "A 3V 100MHz, 35mW, Dynamic Line Memory Macro Cell for HDTV Applications".

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