Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-07-31
2004-04-06
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S065000, C365S149000
Reexamination Certificate
active
06717838
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to random-accessible semiconductor storage devices and, more particularly, to a nonvolatile semiconductor storage device including a ferroelectric thin-film capacitor.
In recent years, there have been researched and developed storage devices employing ferroelectric thin film in a storage-use capacitor (hereinafter, referred to as ferroelectric memory), some of which have been put into practical use. This type of ferroelectric memory has such features as nonvolatile random accessibility, high-speed write and read, and multi-time rewritability.
The storage device using ferroelectric thin film is currently available in the following first and second modes, roughly, as classified below. In the first place, the first mode is a destructive ferroelectric memory which uses a capacitor having a ferroelectric thin film sandwiched between upper and lower electrodes (hereinafter, referred to as ferroelectric capacitor) and which reads, by a sense amplifier, voltages of bit lines that occur depending on output charge amounts upon applying a voltage to this ferroelectric capacitor.
In this case, output charge amount differs between cases where the direction of spontaneous polarization of the ferroelectric capacitor is inverted by the applied voltage and where not inverted. The ferroelectric memory stores and reads data on the basis that polarization in the direction of this inversion or non-inversion is taken as data of “1” or “0.”
Two types are available for this ferroelectric memory as the first mode, i.e., 1T1C type ferroelectric memory which uses one ferroelectric capacitor and one selector transistor for one piece of information like DRAM (Dynamic Random Access Memory) and 2T2C type ferroelectric memory which uses two ferroelectric capacitors and two selector transistors for the same.
In the 1T1C type ferroelectric memory, a read voltage is applied to ferroelectric capacitors of selected memory cells for driving, and charges in amounts corresponding to data that have previously been written in the ferroelectric capacitors are outputted to bit lines for data read by a sense amplifier. For this operation, a reference voltage for comparison with the sense amplifier needs to be generated with a dummy cell (reference cell) or the like. It is noted that the reference voltage is required to fall between the voltages corresponding to “1” and “0,” desirably being just intermediate therebetween for the ensuring of margin.
Now basic properties of a semiconductor storage device using the 1T1C type ferroelectric memory are explained.
As a voltage is applied to between first and second electrodes of the ferroelectric capacitor, in which a ferroelectric thin film is sandwiched by the first and second electrodes, the amount of polarization of the ferroelectric capacitor draws a hysteresis loop as shown in FIG.
7
. In
FIG. 7
, increasing a drive voltage VD from the state of a point A (drive voltage VD=0) causes the amount of polarization of the ferroelectric to increase nonlinearly as indicated by arrows so as to reach a point B (VD=maximum drive voltage VD
MAX
). Further, lowering the drive voltage VD back to 0 causes the amount of polarization to draw a curve BC different from the curve AB so as to reach a point C. Furthermore, applying the drive voltage in the negative direction causes the amount of polarization to reach a point D at a minimum drive voltage (−VD
MAX
), and returning the drive voltage VD again to 0 causes the amount of polarization to return to the original point A.
Consequently, depending on the hysteresis of the applied voltage, the ferroelectric capacitor can take different amounts of polarization like the point A or the point B even with no voltage applied. In this case, assuming the state of point A as a logical “1” and the state of point C as a logical “0” makes it possible to hold two values in a state that the applied voltage is zero.
That is, this ferroelectric memory fulfills a nonvolatile memory that needs no refresh operations or a low power consumption memory that requires fewer refresh operations than DRAMs by using the above hysteretic property. Whereas write operation on the ferroelectric memory is performed by applying a drive voltage to the electrodes of the ferroelectric capacitor as described above, read operation thereon is done similarly by applying a voltage to the ferroelectric capacitor.
In this connection, in conventional 1T1C type ferroelectric memories, a bit line and a drive line to which the ferroelectric capacitor is connected via the selector transistor are controlled prior to a read operation so as to be equal in potential to each other, so that the bit line is already in a floating state at the time of the read operation. In this case, given a capacitance Cf of the ferroelectric capacitor and a wiring capacitance Cb of the bit line, the resultant equivalent circuit is as shown in FIG.
8
.
Then, when the drive voltage VD is applied to a drive line DL, a relational expression of a voltage Vb of a bit line BL can be expressed as follows, where the amount of charges stored in the ferroelectric capacitor is assumed to be Q:
Q=Cf
(
VD−Vb
)=
CfVf
Q=CbVb
where Cf is the nonlinear capacitance inherent in the ferroelectric and Vf is the voltage actually applied to the ferroelectric capacitor.
From these equations, it can be understood that with respect to the voltage Vb outputted to the bit line BL, actual Q and Vb can be determined from an intersecting point between a hysteresis graph of the performance chart showing Q-V characteristics of the ferroelectric capacitor and a load line passing through a point (V,Q)=(VD,0) with a gradient of −Cb.
Accordingly, in a state that a logical “1” has been written, turning ON the switch (selector transistor) so that VD goes “H” results in performance line and load line transitions as shown in
FIG. 9
, showing that an actual result of (Vf,Vb,Q)=(Vf1,Vb1,Q1) can be determined from an intersecting point A1. Likewise, in a state that a logical “0” has been written, turning ON the switch (selector transistor) so that VD goes “H” results in transitions as shown in
FIG. 10
, allowing (Vf,Vb,Q)=(Vf0,Vb0,Q0) to be determined from charge amount and voltage at an intersecting point A0. In this connection, since the voltage Vb1 and the voltage Vb0 take different values from each other, enough voltage difference therebetween allows data read by a sense amplifier SA or the like to be achieved.
On the other hand, in the 2T2C type ferroelectric memory, spontaneous polarizations in different directions have been written in a set of two ferroelectric capacitors, respectively, and inverted or noninverted charges of amounts resulting from driving the individual ferroelectric capacitors are outputted to a bit line and a bit line bar, where levels of those voltages are compared with each other for achievement of data read. For this purpose, the 2T2C type ferroelectric memory has a margin about double that of the 1T1C type ferroelectric memory.
Next, the second mode employs ferroelectric thin film instead of gate oxide of the gate transistor, being also called MFS-FET (Metal/Ferroelectric/Semiconductor—Field Emission Transistor) or 1-transistor (1T) type ferroelectric memory. In this second mode, data storage and read are enabled by determining whether to turn ON or OFF the transistors by using carriers induced to the semiconductor by spontaneous polarizations of the ferroelectrics.
In the case of the 1T type ferroelectric memory, since read is carried out in a static state, nondestructive read is enabled.
However, these 1T1C type ferroelectric memory and 2T2C type ferroelectric memory as the first mode of the prior art have a problem as shown below. That is, the 1T1C type ferroelectric memory and the 2T2C type ferroelectric memory are of the method that involves outputting a remanent polarization amount of the ferroelectric capacitor to a bit line and reading the level of a voltage outputted to the bit lin
Auduong Gene
Nixon & Vanderhye P.C.
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