Semiconductor storage device with common data line structure

Details Semiconductor storage device with common data line structure Semiconductor storage device with common data line structure

1990-01-16

1991-01-08

Bowler, Alyssa H.

Static information storage and retrieval

Systems using particular element

Flip-flop

365203, 365 51, 36518901, G11C 1140, G11C 11407, G11C 700

Patent

active

049842013

ABSTRACT:
Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state. Prior to a reading operation, the data lines are precharged to the first power-source voltage level, or ground potential, and the common data line is precharged to a second power-source voltage level, such as the supply voltage of the memory.

REFERENCES:
patent: 4768172 (1988-08-01), Sasaki
patent: 4802122 (1989-01-01), Avvinen et al.
patent: 4807194 (1989-02-01), Yamada et al.

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