Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
1999-12-15
2001-04-24
Fears, Terrell W. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S229000
Reexamination Certificate
active
06222779
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor storage device which has an automatic write/erase function, and uses an external high voltage or a voltage obtained by boosting a power supply voltage upon write and erase.
A semiconductor storage device with an automatic write/erase function, e.g., a flash EEPROM, can write input data up to its internal predetermined threshold voltage in a memory cell designated by an input address by automatically discriminating the input data, upon reception of a command indicative of, e.g., a write mode. A memory cell which is written with data and has a high threshold voltage is defined by “
0
”, and a memory cell with a low threshold voltage is defined by “
1
”. This write function is similarly used in a pre-programming operation being performed during the erase mode.
FIG. 36
is a schematic block diagram showing the circuit arrangement of a conventional flash EEPROM with the automatic write function. Referring to
FIG. 36
, reference numeral
11
denotes a memory cell array. In this memory cell array
11
, each row of memory cells is selected by a row decoder
12
, and each column of memory cells is designated by a column decoder
13
D via a Y selector
13
S. An address signal is supplied to an address register
14
, multiplexer
15
, and command register
16
. The output signal from the address register
14
is supplied to the multiplexer
15
, and selection signals from the multiplexer
15
are supplied to the row and column decoders
12
and
13
. Data in a memory cell selected by the row and column decoders
12
and
13
is supplied to, and sensed and amplified by a sense amplifier
17
via the Y selector
13
S, and the amplified data is read out via an I/O buffer
18
. On the other hand, write data input to the I/O buffer
18
is latched by a data register
19
, and the data latched by the data register
19
is written in a memory cell selected by the row and column decoders
12
and
13
via a write data generation circuit
20
and write switch
21
. The write data generation circuit
20
receives the output signal from the sense amplifier
17
and is controlled to generate write data.
The command register
16
receives a control signal and command, and its output signal is supplied to the data register
19
and a control circuit
22
. The control circuit
22
controls the operation mode of the flash EEPROM and the like in accordance with the control signal and command supplied to the command register
16
, and a timer
23
, power supply circuit (booster circuit)
24
, verify circuit
25
, and the like are controlled by the output signal from the control circuit
22
. The time measurement output of the timer
23
is supplied to the control circuit
22
. The power supply circuit
24
shifts the level of a power supply voltage (i.e., boosts it), and supplies high voltages for write to the row and column decoders
12
and
13
, write data generation circuit
20
, write switch
21
, and the like. The verify circuit
25
receives the output signal from the write data generation circuit
20
, and supplies a verify result to the control circuit
22
.
In the above arrangement, upon reception of a write command, the command register
16
recognizes a write mode, and data input to the I/O buffer
18
and an address signal are respectively held by the data register
19
and address register
14
. The multiplexer
15
selects the address signal held by the address register
14
, and supplies it to the row and column decoders
12
and
13
. By respectively decoding row and column addresses by the row and column decoders
12
and
13
, a memory cell corresponding to the input address is selected.
Upon reception of an establishment signal from the command register
16
, the control circuit
22
begins to operate, and its internal control enters a write verify state. After an elapse of a setup time set in the timer
23
, the control circuit
22
reads out data from the written memory cell and compares the readout data with input data. As a result of comparison, if the written data matches the readout data, it is determined that write is satisfactorily done, and write operation ends; otherwise, if the two data do not match, rewrite is started based on the written data (only bits that are “
0
” in the input data but “
1
” in the readout data are rewritten).
More specifically, as shown in the flow chart in
FIG. 37A
, when write verify is started, a write verify setup is made (step S
1
), and a write verify read is done (step S
2
) after an elapse of a power supply setup period around 1 &mgr;s. It is checked by comparison if the input data matches the readout data (step S
3
). If the two data match each other, a read setup is done (step S
4
), thus ending the process. On the other hand, if the two data do not match, it is checked if the number of rewrite cycles has reached a limit (step S
5
). If NO in step S
5
, the input data and inverted data of the readout data are ANDed to obtain write data (step S
6
). The input data, readout data, and write data in step S
6
have a logic relationship shown in FIG.
37
B. Subsequently, write is done (step S
7
). In this write operation, the voltage supplied to the memory cell is a high voltage obtained by boosting a power supply voltage V
DD
(e.g., 3V) by the power supply circuit
24
. As shown in the timing chart in
FIG. 38
, for example, a voltage of 10V is applied to the control gate (word line) of a selected cell transistor, and a voltage around 5V to 6V is applied to its drain (bit line). The write method to this cell transistor is hot electron injection, and a drain current around 500 &mgr;A/bit is required. A write continues for a write time, e.g., about 5 &mgr;s, set in the timer
23
. After that, the number of cycles is incremented by 1 (step S
8
), and the flow returns to step S
1
to repeat the aforementioned write verify process until the input data matches the readout data. If the two data do not match even after the number of cycles has reached a predetermined limit, a defect is determined (step S
9
), and a read setup is done (step S
4
), thus ending the process.
Since all currents required in the above-mentioned write verify process are supplied from the power supply circuit (booster circuit)
24
, currents obtained by multiplying currents consumed by memory cells by efficiency are required. Assuming that the output voltage of the power supply circuit
24
is constant, the booster efficiency lowers as the power supply voltage V
DD
boosted by the power supply circuit
24
is lower. Normally, the current supply performance of the power supply circuit
24
is nearly proportional to the area of the capacitor in the charge pump circuit in this circuit
24
. Hence, when the power supply voltage V
DD
is lowered while the output voltage (boosted voltage) upon writing data in a memory cell remains the same, the area of the capacitor must be increased in correspondence with the current supply performance drop of the power supply circuit
24
, resulting in an increase in chip area.
As described above, in the conventional semiconductor storage device which has the automatic write function and uses a high voltage obtained by boosting a power supply voltage upon write, if the power supply voltage drops, the current supply performance of the booster circuit that generates a high voltage for write lowers, resulting in a long write time.
When the lowered power supply voltage is designed to use, the area of the capacitor must be increased in correspondence with the current supply performance drop of the booster circuit, resulting in a large chip area.
On the other hand, in an electrically data rewritable flash EEPROM, data is erased in units of erase blocks. This process includes a series of operations such as pre-erase write (pre-programming) for setting all cells in a given block in a write state, batch-erase/over-erase verify processes of a block, and the like.
However, when automatic erase is done for a block which had been erased previously and has not undergone any write, i.e
Hara Tokumasa
Kato Hideo
Saito Hidetoshi
Tomita Naoto
Fears Terrell W.
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
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