Semiconductor storage device using a bitline GND sensing...

Details Semiconductor storage device using a bitline GND sensing... Semiconductor storage device using a bitline GND sensing...

2007-01-17

2010-06-01

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Read/write circuit

Particular read circuit

C365S189110, C365S196000, C365S204000, C365S145000

Reexamination Certificate

active

07729181

ABSTRACT:
A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.

REFERENCES:
patent: 6421268 (2002-07-01), Kato et al.
patent: 6487103 (2002-11-01), Yamamoto et al.
patent: 6661697 (2003-12-01), Yamamoto et al.
patent: 6856560 (2005-02-01), Rehm et al.
patent: 6906975 (2005-06-01), Kang et al.
patent: 2005/0195639 (2005-09-01), Fukushi et al.
patent: 2002-133857 (2002-05-01), None
patent: 2005-293818 (2005-10-01), None
Shoichiro Kawashima, “Bitline GND Sensing Technique for Low-Voltage Operation FeRAM”, IEEE Journal of Solid-State Circuits, vol. 37, No. 5, May 2002, pp. 592-598.

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