Semiconductor storage device, test method therefor, and test...

Details Semiconductor storage device, test method therefor, and test... Semiconductor storage device, test method therefor, and test...

2007-03-20

2007-03-20

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233500, C365S201000

Reexamination Certificate

active

10498398

ABSTRACT:
A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal. By controlling a timing for generating the first testing refresh pulse generation signal, it is possible to generate a read or write operation and a refresh operation so that there is a predetermined time interval between these operations.

REFERENCES:
patent: 5424990 (1995-06-01), Ohsawa
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patent: 6272588 (2001-08-01), Johnston et al.
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patent: 63-206994 (1988-08-01), None
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patent: 4-74349 (1992-03-01), None

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