Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2010-02-04
2011-11-08
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S205000, C365S185250
Reexamination Certificate
active
08054697
ABSTRACT:
A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BLBwhen a sense amplifier starts to read potential of the bit lines. The level shift unit includes level shifting capacitors and a timing generator. Each of level shifting capacitors have one electrode connected to each bit line and form one pair by two level shifting capacitors for each bit line pair. The timing generator is connected to each of the other electrodes of the level shifting capacitors in common, and supplies a shift capacitor drive signal to a common node of the other electrodes, so as to change stored electricity amount of the level shifting capacitors at a predetermined timing.
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J. Barth, et al., “A 300 MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write”, ISSCC 2002/Session 9/DRAM and Ferroelectric Memories/9.3, 2002 IEEE International Solid-State Circuits Conference, Feb. 5, 2002.
McGinn IP Law Group PLLC
Nguyen Tuan T.
Renesas Electronics Corporation
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