Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-12-27
2004-12-07
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S189070, C365S054000, C365S189040, C365S185180, C365S185270
Reexamination Certificate
active
06829179
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a static random access memory (SRAM) which is a semiconductor storage device, and more particularly to a semiconductor storage device of low power dissipation which has a high integration degree and which performs a high-speed operation.
In general, a memory cell in a prior-art SRAM is constructed of bit lines BL and BLb which pair with each other, a data retention circuit which includes a first CMOS inverter that is constituted by a first P-channel type MOS transistor (hereinbelow, termed “PMOS”) connected to a first node N
1
and a supply potential Vdd, as well as a first N-channel type MOS transistor (hereinbelow, termed “NMOS”) connected to the first node N
1
and a ground potential Vbb, and a second CMOS inverter that is constituted by a second PMOS connected to a second node N
2
and the supply potential Vdd, as well as a second NMOS connected to the second node N
2
and the ground potential Vbb, that is operated by receiving the output of the first CMOS inverter and that delivers its output as the input of the first CMOS inverter, and a first or second control transistor which is connected to a word line WL and which renders the path between the bit line BL or BLb and the first or second node N
1
or N
2
electrically conductive or nonconductive.
That is, the memory cell in the prior-art SRAM is constructed of the six MOS (Metal Oxide Semiconductor) transistors.
In the operation of writing data into such a memory cell in the prior-art SRAM, the word line WL is activated to an H level, whereby the first and second control transistors are brought into their ON states, and write data afforded to the bit lines BL and BLb beforehand are respectively written into the first node N
1
and second node N
2
of the data retention circuit.
In case of writing “data 1” into the first node N
1
, the input/output characteristics curve of the first CMOS inverter
102
and that of the second CMOS inverter
103
have a single intersection point (stable point) for a potential corresponding to the “data 1” f or example, the first supply potential (Vdd), whereas in case of writing “data 0” into the first node N
1
, the input/output characteristics curve of the first CMOS inverter
102
and that of the second CMOS inverter
103
have a single intersection point (stable point) for a potential corresponding to the “data 0”, for example, the ground potential (VGND).
In this manner, each of the operations of writing the data into the first node N
1
of the data retention circuit constructed of the two inverters is implemented in the case where both the input/output characteristics curves have the single intersection point.
Besides, during a data retention period, the first and second control transistors are held in their OFF states, and data written into the first and second nodes N
1
, N
2
are latched in the flip-flop constructed of the first and second CMOS inverters, whereby the data are retained.
Further, in the operation of reading data out of the memory cell, the word line WL is first activated to the H level, thereby to bring the first and second control transistors into their ON states, and potentials corresponding to data held in the first node N
1
and the second node N
2
are respectively outputted to the bit lines BL and BLb held in their high-impedance states. Thereafter, the difference between the potentials outputted to the respective bit lines BL and BLb is amplified by a sense amplifier, whereby the data is read out.
SUMMARY OF THE INVENTION
The prior-art semiconductor storage device, however, has posed the problem that each memory cell is constructed of the six MOS transistors, so regions each serving to form the six elements are necessitated on a semiconductor substrate in accordance with the number of the memory cells which are to be arrayed in the semiconductor storage device. Especially in the prior-art semiconductor storage device, the two, first and second control transistors are required for controlling the write or read of data into or from the data retention circuit, so that regions for forming these transistors are necessitated on the semiconductor substrate. That is, the prior art has involved the problem that a layout area increases. Besides, in the prior-art semiconductor storage device, data is written or read using the two bit lines BL and BLb, so that current for the two bit lines is dissipated in the memory cell operation. This has resulted in the problem that the dissipation current in the operation increases to make lower power dissipation difficult.
In order to solve the above problems, a semiconductor storage device according to the present invention comprises a first reference voltage terminal which supplies a first potential that is a predetermined logic level; a second reference voltage terminal which supplies a second potential that is lower than the first potential, and that is a logic level different from the predetermined logic level; a first node; a first control transistor which is connected between a bit line and the first node, and whose control terminal is connected to a word line; a data retention circuit which includes a first transistor that is connected between the first node and the second reference voltage terminal, and that has its control terminal connected to a second node, and a first inverter that includes a second transistor connected between the second node and the second reference voltage terminal, having its input terminal connected to the first node, having its output terminal connected to the control terminal of the first transistor, and outputting to the output terminal a voltage correspondent to the logic level different from the logic level inputted to the input terminal; and a substrate potential control circuit which selectively alters a substrate potential of the first transistor so as to make a threshold voltage of the first transistor higher as compared with threshold voltages of the first control transistor and the second transistor.
Besides, another semiconductor storage device according to the present invention comprises a first reference voltage terminal which supplies a first potential that is a predetermined logic level; a second reference voltage terminal which supplies a second potential that is lower than the first potential, and that is a logic level different from the predetermined logic level; a first node; a first control transistor which includes a first channel region connected between a bit line and the first node, and whose control terminal is connected to a word line; and a data retention circuit which includes a first transistor that includes a second channel region connected between the first node and the second reference voltage terminal, and that has its control terminal connected to a second node, and a first inverter that includes a second transistor including a third channel region connected between the second node and the second reference voltage terminal, having its input terminal and its output terminal respectively connected to the first node and to the control terminal of the first transistor, and outputting to the output terminal a voltage correspondent to the logic level different from the logic level inputted to the input terminal; wherein an impurity concentration of the second channel region is higher as compared with impurity concentrations of the first and third channel regions.
In addition, still another semiconductor storage device according to the present invention comprises a first reference voltage terminal which supplies a first potential that is a predetermined logic level; a second reference voltage terminal which supplies a second potential that is lower than the first potential, and that is a logic level different from the predetermined logic level; a first node; a first control transistor which is connected between a first bit line and the first node, and whose control terminal is connected to a word line; a second node; a second control transistor which is connected between a second bit line and the second node,
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
Yoha Connie C.
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