Semiconductor storage device having redundancy area

Details Semiconductor storage device having redundancy area Semiconductor storage device having redundancy area

2008-12-11

2011-12-06

Lappas, Jason (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

08072827

ABSTRACT:
A semiconductor storage device is provided with: a memory cell array which includes a normal area and a redundancy area which replaces a defective memory cell in the normal area; a normal area refresh circuit which performs a CBR refresh operation of a memory cell which is connected to a word line in the normal area; and a redundancy area refresh circuit which performs a CBR refresh operation of a memory cell which is connected to a word line in the redundancy area in parallel with the CBR refresh operation of the memory cell in the normal area.

REFERENCES:
patent: 5652725 (1997-07-01), Suma et al.
patent: 6590815 (2003-07-01), Mine
patent: 2002/0080657 (2002-06-01), Mine
patent: 2002-124096 (2002-04-01), None

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