Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate
2002-07-25
2004-06-29
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
C257S393000
Reexamination Certificate
active
06756692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor storage devices, and particularly to the structure of a semiconductor storage device having SRAM (Static Random Access Memory) memory cells.
2. Description of the Background Art
FIG. 24
is a circuit diagram showing the structure of a conventional SRAM memory cell. The NMOS transistors Q
1
and Q
4
are transistors for driving (referred to also as “driver transistors”) and the NMOS transistors Q
3
and Q
6
are transistors for accessing (referred to also as “access transistors”). The PMOS transistors Q
2
and Q
5
are transistors for load (load transistors); the PMOS transistors Q
2
and Q
5
may be replaced by resistor elements.
The NMOS transistors Q
1
and Q
4
have their respective sources connected to a power supply
2
which gives a GND potential. The PMOS transistors Q
2
and Q
5
have their respective sources connected to a power supply
1
which gives a given power-supply potential (Vdd). The NMOS transistor Q
1
and the PMOS transistor Q
2
have their respective drains connected to a storage node ND
1
. The NMOS transistor Q
4
and the PMOS transistor Q
5
have their respective drains connected to a storage node ND
2
. The storage node ND
1
is connected to the gates of the NMOS transistor Q
4
and the PMOS transistor Q
5
. The storage node ND
2
is connected to the gates of the NMOS transistor Q
1
and the PMOS transistor Q
2
. The NMOS transistor Q
3
has its gate connected to a word line WL, its source connected to the storage node ND
1
, and its drain connected to a bit line BL
0
. The NMOS transistor Q
6
has its gate connected to the word line WL, its source connected to the storage node ND
2
, and its drain connected to a bit line BL
1
.
FIG. 25
is a top view schematically showing the structure of the conventional SRAM memory cell. Element isolation insulating film
4
is partially formed on a silicon substrate to define element formation regions. The NMOS transistor Q
1
shown in
FIG. 24
has a source region
5
and a drain region
6
, both of which are n
+
type. The PMOS transistor Q
2
has a source region
8
and a drain region
9
, both of which are p
+
type. The NMOS transistor Q
4
has a source region
10
and a drain region
11
, both of which are n
+
type. The PMOS transistor Q
5
has a source region
13
and a drain region
14
, both of which are p
+
type. The NMOS transistor Q
3
has a source region
6
and a drain region
15
, both of which are n
+
type, and the NMOS transistor Q
6
has a source region
11
and a drain region
16
, both of which are n
+
type.
The NMOS transistor Q
1
and the PMOS transistor Q
2
have a common gate structure
7
, the gate structure
7
being connected to the drain regions
11
and
14
of the NMOS transistor Q
4
and the PMOS transistor Q
5
. The NMOS transistor Q
4
and the PMOS transistor Q
5
have a common gate structure
12
, the gate structure
12
being connected to the drain regions
6
and
9
of the NMOS transistor Q
1
and the PMOS transistor Q
2
. The NMOS transistors Q
3
and Q
6
have a common gate structure
17
, which functions as the word line WL.
The conventional semiconductor storage device thus constructed is prone to a phenomenon (soft error) in which stored information is upset when ionizing radiation, such as alpha (&agr;) rays emitted from the package material etc., enters the memory cells.
For example, referring to
FIG. 24
, suppose that the potential at the storage node ND
1
is at a high level and the potential at the storage node ND
2
is at a low level. Under this condition, when an alpha-ray is incident in the drain of the NMOS transistor Q
1
, the alpha-radiation generates a large number of electron-hole pairs and the electrons are collected by the drain of the NMOS transistor Q
1
, which causes the potential at the storage node ND
1
to change from the high level to the low level. The potential change at the storage node ND
1
is then transferred to the NMOS transistor Q
4
and the PMOS transistor Q
5
, causing the potential at the storage node ND
2
to change from the low level to the high level. The potential change at the storage node ND
2
is then transferred to the NMOS transistor Q
1
and the PMOS transistor Q
2
. The information stored in the semiconductor storage device is thus destroyed.
SUMMARY OF THE INVENTION
An object of the present invention is to obtain a semiconductor storage device having high soft-error immunity.
According to a first aspect of the present invention, a semiconductor storage device includes a static random access memory cell which includes a first driver transistor, a first load element, and a first access transistor which are connected to each other through a first storage node, and a second driver transistor, a second load element, and a second access transistor which are connected to each other through a second storage node, the first driver transistor having a first gate electrode connected to the second storage node, the second driver transistor having a second gate electrode connected to the first storage node. The semiconductor storage device further includes a first protection film formed to cover part of the first gate electrode. Part of the first gate electrode which is not covered by the first protection film has a structure in which a first semiconductor layer and a first metal-semiconductor compound layer are stacked in this order on a first gate insulating film. The part of the first gate electrode which is covered by the first protection film has a structure in which the first semiconductor layer is formed on the first gate insulating film and the first metal-semiconductor compound layer is not formed on the first semiconductor layer.
The second storage node is connected to the first driver transistor through a high resistance portion of the first gate electrode which is covered by the first protection film and where the first metal-semiconductor compound layer is absent. This enhances the soft-error immunity of the semiconductor storage device.
According to a second aspect of the invention, another semiconductor storage device includes a static random access memory cell which includes a first driver transistor, a first load element, and a first access transistor which are connected to each other through a first storage node, and a second driver transistor, a second load element, and a second access transistor which are connected to each other through a second storage node, the first driver transistor having a first gate electrode connected to the second storage node, the second driver transistor having a second gate electrode connected to the first storage node. The semiconductor storage device further includes a first resistance-adding transistor having a first impurity-containing region connected to the first gate electrode and a second impurity-containing region connected to the second storage node, and the first gate electrode is connected to the second storage node through the first resistance-adding transistor.
The first gate electrode is connected to the second storage node through the first resistance-adding transistor, which enhances the soft-error immunity of the semiconductor storage device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
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patent: 5373170 (1994-12-01), Pfiester et al.
patent: 5395783 (1995-03-01), Baumann et al.
patent: 5422499 (1995-06-01), Manning
patent: 6020242 (2000-02-01), Tsai et al.
patent: 6429124 (2002-08-01), Tang et al.
patent: 690 09 157 (1994-09-01), None
patent: 0 432 057 (1991-06-01), None
patent: 5-235301 (1993-09-01), None
patent: 6-188388 (1994-07-01), None
Ross A. Kohler, et al., “Seu Characterization of Hardened CMOS SRAMS Using Statistical Analysis of Feedback Delay in Memory Cells”, IEEE Transactions on Nuclear Science, vol. 36, No. 6, Dec. 1989, pp. 2318-2
Hirano Yuuichi
Ipposhi Takashi
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
Wilson Allan R.
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