Semiconductor storage device having four-transistor memory...

Details Semiconductor storage device having four-transistor memory... Semiconductor storage device having four-transistor memory...

2000-10-13

2002-04-16

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S904000, C257S903000

Reexamination Certificate

active

06373107

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device having four-transistor memory cells to save an area.
2. Description of the Related Art
Conventionally, a memory cell of a static random access memory (SRAM) is provided with two access transistors and four driver transistors.
As such an SRAM device, the one with access at a higher speed is proposed (Japanese Patent Laid-Open Publication No. Hei 9-270468). In the conventional SRAM device disclosed in this publication, gate electrodes of six transistors constituting one memory cell are extended substantially in the same direction. Consequently, access can be performed at a high speed since an occupied area of the memory cell is reduced and the bit line length is shortened. Two access transistors in one memory cell are disposed at either end parts of the memory cell, respectively, in the longitudinal direction. Each access transistor is provided with contact plugs for supplying signals from word lines (metal interconnect lines) in the upper layer. Bit lines are extended in the short direction of the memory cell while word lines are extended in the direction perpendicular thereto.
An SRAM device with a reduced element area has been proposed (Japanese Patent Laid-Open Publication No. Hei 10-178110). In the conventional SRAM device disclosed in this publication, gate electrodes of six transistors constituting one memory cell are also extended substantially in the same direction. Two access transistors in one memory cell are disposed at either end parts, respectively, of the memory cell in the longitudinal direction. Contact plugs for supplying signals from word line (metal interconnect line) in the upper layer to the access transistors are shared between two neighboring memory cells. Therefore, two memory cells have two contact plugs each. In this conventional SRAM device, word lines are extended in the longitudinal direction of the memory cell while the bit lines are extended in the direction perpendicular thereto.
Recently, an SRAM cell composed of four transistors has been proposed (Japanese Application Publication No. Hei 10-346149).
FIG. 1
is a circuit diagram showing a conventional SRAM cell.
In the conventional SRAM cell composed of four transistors, in one memory cell provided are access transistors Tr
101
and Tr
102
of which sources are connected to two bit lines BL
101
and BL
102
, respectively, constituting a bit line pair. The access transistors Tr
101
and Tr
102
are p-channel MOS transistors. A word line WL
101
is connected to respective gates of the access transistor Tr
101
and Tr
102
.
Also provided is a driver transistor Tr
103
of which drain is connected to the drain of the access transistor Tr
101
and of which gate is connected to the drain of the access transistor Tr
102
. Further provided is a driver transistor Tr
104
of which drain is connected to the drain of the access transistor Tr
102
and of which gate is connected to the drain of the access transistor Tr
101
. The driver transistor Tr
103
and Tr
104
are n-channel MOS transistor. The sources of the driver transistor Tr
103
and Tr
104
are grounded.
FIG. 2A
is schematic view showing a relationship between a gate electrode and a diffused layer in each transistor of the conventional SRAM cell and the contact plugs connected thereto.
FIG. 2B
is a schematic view showing a relationship between a first metal interconnect layer of the conventional SRAM cell and the contact plugs connected therebeneath.
FIG. 3
is a sectional view along line C—C in
FIGS. 2A and 2B
.
In the conventional SRAM cell, as shown in
FIG. 2A
, the access transistors Tr
101
and Tr
102
are disposed side by side in the short direction at one end part in the longitudinal direction. The driver transistors Tr
103
and Tr
104
are disposed in this order over the end part on the side opposite to the side of the access transistors Tr
101
and Tr
102
in the longitudinal direction.
This conventional SRAM cell is provided with a gate poly-silicon layer G
101
constituting the gate electrodes of the access transistor Tr
101
and Tr
102
. The gate poly-silicon layer G
101
is extended in the short direction of the cell. The gate poly-silicon layer G
101
is shared among a plurality of SRAM cells arrayed in the short direction and constitutes the word line WL
101
of these SRAM cells. Further, gate poly-silicon layers G
103
and G
104
are provided to constitute the gate electrodes of the driver transistors Tr
103
and Tr
104
, respectively.
In addition, a contact plug CS
101
is provided on a source diffused layer S
101
of the access transistor Tr
101
and a contact plug CD
101
is provided on a drain diffused layer D
101
of the access transistor Tr
101
. Similarly, a contact plug CS
102
is provided on a source diffused layer S
102
of the access transistor Tr
102
and a contact plug CD
102
is provided on a drain diffused layer D
102
of the access transistor Tr
102
. A contact plug CS
103
is provided on a source diffused layer S
103
of the driver transistor Tr
103
and a contact plug CD
103
is provided on a drain diffused layer D
103
of the driver transistor Tr
103
. Furthermore, a contact plug CS
104
is provided on a source diffused layer S
104
of the driver transistor Tr
104
and a contact plug CD
104
is provided on a drain diffused layer D
104
of the driver transistor Tr
104
.
The gate poly-silicon layer G
103
is connected to the drain diffused layer D
102
of the access transistor Tr
102
via the contact plug CD
102
and connected to the drain diffused layer D
104
of the driver transistor Tr
104
via the contact plug CD
104
. The gate poly-silicon layer G
104
is connected to the drain diffused layer D
101
of the access transistor Tr
101
via the contact plug CD
101
and connected to the drain diffused layer D
103
of the driver transistor Tr
103
via the contact plug CD
103
.
As shown in
FIG. 3
, a sidewall insulating layer
102
is formed on the side of each gate poly-silicon layer except for portions with which the contact plugs are in contact. A gate oxide film
105
is formed between each gate poly-silicon layer and the p-type semiconductor substrate
101
. An n-well
104
is formed at the surface of a semiconductor substrate
101
in a region in which the access transistors Tr
101
and Tr
102
are provided. Further, an embedded field insulating layer
103
is selectively formed between the transistors. First and second interlayer insulating layers
151
and
152
for coating the entire surface of these gate poly-silicon layers, diffused layers and the like are formed in this order. The contact plugs CD
101
, CD
102
, CD
103
and CD
104
provided on the drain diffused layer of each transistor are formed only in the first interlayer insulating layer
151
.
Furthermore, as shown in
FIGS. 2B and 3
, a first metal interconnect layer
161
is provided on the second interlayer insulating layer
152
. A ground layer
112
connected to the contact plugs CS
103
and CS
104
is formed in the first metal interconnect layer
161
. Interconnect layers
113
a
and
113
b
connected to the contact plug CS
101
and CS
102
, respectively, are also formed in the first metal interconnect layer
161
.
Furthermore, a third interlayer insulating layer
153
is formed on the second interlayer insulating layer
152
and first metal interconnect layer
161
. Through holes are formed at positions coinciding with the interconnect layers
113
a
or
113
b
in the third interlayer insulating layer
153
and conductive layers
114
are embedded in the through holes. Further, as shown in
FIG. 3
, a second metal interconnect layer
162
is provided on the third interlayer insulating layer
153
. Two bit lines BL
101
and BL
102
connected to each conductive layer
114
are formed in the second metal interconnect layer
162
. The bit lines BL
101
and BL
102
are extended in the longitudinal direction of the cell and are shared among a plurality of SRAM cells disposed along the direction.
The threshold voltage of the dr

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