Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2005-04-12
2005-04-12
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100, C365S189090, C365S236000
Reexamination Certificate
active
06879537
ABSTRACT:
An operation control circuit is provided for shortening a transition time from a deep stand-by mode to a stand-by mode in a pseudo-SRAM having the deep stand-by mode and the stand-by mode. The transition from the deep stand-by mode to the stand-by mode starts first and second timer circuits which respectively output a timer output TN of a constant cycle needed for self-refresh and a timing signal TR of a shorter cycle than a self-refresh cycle. A counter circuit counts the output TR from the second timer circuit immediately after the deep stand-by mode has been transitioned to the stand-by mode. If the counted value corresponds to a value as set, then the counter circuit outputs an operation mode switching signal. A selector circuit comprising a multiplexer is switched and controlled by the output from the counter circuit. The selector circuit remains selecting TR until the counted value of the counter circuit corresponds to the set value, and in the subsequent stand-by mode, the selector circuit selects and outputs TN.
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Nakagawa Atsushi
Takahashi Hiroyuki
Choate, Hall & StewartLLP
Lebentritt Michael S.
NEC Electronics Corporation
Nguyen Tuan T.
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