Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-10-24
2001-07-10
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S190000, C365S193000, C365S194000, C365S196000
Reexamination Certificate
active
06259640
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device including a detecting circuit capable of detecting a shortcircuit between a storage node in a memory cell and a transistor gate, in particular, a high resistance shortcircuit therebetween.
2. Description of the Related Art
In a semiconductor storage device using a DRAM shown in
FIG. 12
, for example, when a voltage is applied to a gate TG of a transistor
101
in a memory cell
100
, the transistor
101
is turned ON and electric charges stored in a capacity
102
are fed to a bit line BL through a storage node SN, accompanied by change of the electric potential of the bit line BL. A sense amplifier (not shown) serves to recognize the electric potential and to output the electric potential as magnitude data.
In the process of manufacturing the memory cell for the semiconductor storage device, a shortcircuit has been caused between the gate TG of the transistor
101
constituting the memory cell
100
or between the gate TG and the storage node SN due to an etching residue or a foreign substance in some cases. The memory cell is not operated well due to the shortcircuit. In order to eliminate this drawback, it has been necessary to detect the shortcircuited memory cell. For example, in the case in which the storage node SN and the gate TG of the transistor
101
are shortcircuited due to a substance having a low resistance, the shortcircuit can easily be detected because the electric potential of the gate TG is transmitted to the storage node SN, resulting in inversion of the electric potential level at the storage node SN.
However, in the case of a high resistance shortcircuit caused by a foreign substance having a high resistance, it has conventionally been difficult to detect the high resistance shortcircuit. In the following description, the “high resistance shortcircuit” implies a shortcircuit caused by a foreign substance having a high resistance which takes a time in transmitting a High-level electric potential at the gate TG of the transistor
101
to the storage node SN to such an extent that the Low-level electric potential at the storage node SN cannot be inverted to the High-level through the High-level electric potential at the gate TG during the operating timing of the conventional sense amplifier.
In the event that the gate TG of the transistor
101
and the storage node SN are shortcircuited with a high resistance due to the contact with the foreign substance, the data reading and sensing operation is completed before the High-level electric potential at the gate TG is transmitted to the storage node SN and inverted during the operation for reading data from the memory cell due to the high resistance shortcircuit during the operation of the conventional sense amplifier when a voltage is applied to the gate TG of the transistor
101
to turn the transistor
101
on and to read the electric potential level at the storage node SN. For this reason, data errors do not occur and the high resistance shortcircuit between the storage node SN and the gate TG cannot therefore be detected.
However, such a high resistance shortcircuit needs to be detected due to the unstable operation of the memory cell. In the conventional art, there have not been methods other than a physical analyzing method such as structural analysis and it has been difficult to detect the high resistance shortcircuit electrically on a circuit bases.
Japanese Patent Laid-Open Publication No. 4-28084 discloses a semiconductor storage device in which the start timing of the operation for detecting a potential difference between a pair of bit lines can be set externally to allow information about a bit line having a small potential difference to be correctly distinguished due to the insufficient capacity of the capacitor of the memory cell and the like so that a device including the bit line can be utilized as a good product. On the other hand, the present invention has an object to detect a high resistance shortcircuit between the gate of the transistor in the memory cell and the storage node, in which the operation timing of the sense amplifier in a test mode or the like is delayed for a predetermined period such that the high resistance shortcircuit can be detected. Thus, the present invention is different from the Japanese Patent Laid-Open Publication No. 4-28084.
Japanese Patent Laid-Open Publication No. 7-85668 discloses a semiconductor storage device which is intended for reducing noises during the operation of a sense amplifier by providing a capacity between an activating control circuit and the sense amplifier to prevent a rapid change in the power source of the sense amplifier. Similarly, Japanese Patent Laid-Open Publication No. 5-144263 discloses a semiconductor storage device in which a plurality of delay circuits constituted by using a resistance and a capacity are provided in a sub-block unit dividing a bit line, the operation timing of the sense amplifiers between banks is shifted and the number of the sense amplifiers operating is simultaneously decreased by utilizing the fact that a time is varied for transmitting a change in the electric potential of the bit line caused by the electric potential of the cell to the sense amplifier according to a distance between word lines selected by the sense amplifier during multi-bank operation so that an instantaneous operating current and noises made during the operation can be reduced, respectively.
Moreover, Japanese Patent Laid-Open Publication No. 62-202398 discloses a semiconductor storage device in which a circuit for detecting that a word line is boosted to have the threshold of a transfer gate of a cell and a sense amplifier is operated in a timing in which the word line is boosted reliably to minimize the delay of a boost time for the word line, thereby increasing a speed.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-mentioned problems and has an object to provide a semiconductor storage device capable of detecting a high resistance shortcircuit between the storage node of a memory cell and the gate of the transistor of the memory cell by delaying the operation timing of a sense amplifier when the high resistance shortcircuit is to be detected.
The present invention provides a semiconductor storage device including an array of memory cells constituted by a capacitor storing an electric charge
10
and a transistor, a sense amplifier section constituted by at least one sense amplifier for distinguishing, as data, the electric charge stored in each of the memory cells, and a sense amplifier control section for controlling operation of the sense amplifier section in which the sense amplifier is delayed by a predetermined time as compared with a normal mode and is operated in a test mode.
According to the present invention, the timing in which the sense amplifier is activated is delayed by a predetermined time in the test mode. Consequently, it is possible to detect a high resistance shortcircuit generated between a storage node in the memory cell and the gate of the transistor. Thus, the detection test of the high resistance shortcircuit is carried out in a wafer test stage so that defective cell can be detected, and furthermore, the defective cell can be replaced with a redundant cell, thereby enhancing the yield of a good product.
According to a preferred embodiment, the sense amplifier control section may include a delay circuit which is preset to a predetermined delay time, and may serve to output, through the delay circuit only in the test mode, a sense amplifier activating signal generated in response to an externally input ROW address strobe signal for activating the sense amplifier. Consequently, it is possible to easily delay the operation timing of the sense amplifier by a predetermined time in the test mode.
Moreover, it is desirable that the predetermined delay time should be at least a time required for changing an electric potential level of a storage node in a memory cell by
Endo Shunsuke
Itou Takashi
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Andrew Q.
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