Semiconductor storage device formed to optimize test...

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S230060, C365S230030, C365S189050, C365S205000, C365S233100

Reexamination Certificate

active

06876588

ABSTRACT:
There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

REFERENCES:
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patent: 5615164 (1997-03-01), Kirihata et al.
patent: 5841710 (1998-11-01), Larsen
patent: 6385071 (2002-05-01), Chai et al.
patent: 6396748 (2002-05-01), Fujita
patent: 6741509 (2004-05-01), Kato et al.
Yohji Watanabe et al., “A 286 mm2256Mb DRAM with x32 Both-Ends DQ”, IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1996, pp 567-574.

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