Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-01-16
2004-05-25
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S230060, C365S230030
Reexamination Certificate
active
06741509
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-009370, filed Jan. 17, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor storage device and more particularly to a semiconductor storage device which is intended to optimize the test technique and redundancy technology.
2. Description of the Related Art
Recently, the storage capacity of the semiconductor storage device keeps on increasing and various test techniques for testing whether or not semiconductor storage devices are correctly operated and redundancy technologies for repairing (compensating for) defects of semiconductor storage devices come to play an important role. In the semiconductor storage device of large storage capacity, it is essential to suppress the test time for making various function tests and enhance the efficiency of the redundancy technology for repairing defects of semiconductor storage devices and lower the cost thereof.
However, it is difficult to optimize the test technique and redundancy technology, and if an attempt is made to test a semiconductor storage device which has been repaired by use of the redundancy technology, the test time becomes longer and the test operation becomes difficult, and if an attempt is made to reduce the test time, the redundancy technology of high efficiency and low cost cannot be applied.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a cell array unit are simultaneously activated, comprising an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not, wherein the word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.
According to another aspect of the present invention, there is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of (2
n
: n is a natural number) elements in a cell array unit are simultaneously activated, comprising n signal lines which transmit signals representing any one of the elements to be activated simultaneously, when is found to be defective and which should be replaced by a row redundant element: and an array control circuit configured to locally decode signals transmitted via the n signal lines, and set an element selected in the plurality of elements into a disable state.
According to still another aspect of the present invention, there is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of (2
n
: n is a natural number) elements in a cell array unit are simultaneously activated, comprising a first signal line which transmits a word line state signal indicating activation and deactivation of the plurality of elements, a second signal line which transmits a signal indicating occurrence of redundancy replacement of the defective element by the row redundant element, n third signal lines which transmit signals having address information indicating which one of the plurality of elements to be activated simultaneously is replaced at the time of replacement of the defective element by the row redundant element if at least one of the plurality of elements is defective, and an array control circuit which is configured to decode the signals transmitted via the n third signal lines for each memory block, wherein the row redundant element is set into an activated state and the defective element is set into a deactivated state and replaced by the row redundant element by use of the array control circuit if at least one of the plurality of elements is defective.
According to an aspect of the present invention, there is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a cell array unit are simultaneously activated, comprising a control circuit configured to hold address and redundancy information in an operation mode of sequentially activating a plurality of word lines at different times, thereby to select the word lines together.
According to an aspect of the present invention, there is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a cell array unit are simultaneously activated, comprising an array control circuit which is configured to set the row redundant element into an activated state, set the defective element into a deactivated state and replace the defective element by the row redundant element if at least one of the plurality of elements is defective, the array control circuit including a first latch circuit configured to hold a present state until a precharge command is received if an array control circuit state signal is received in an operation mode of sequentially activating a plurality of word lines at different times, thereby to activate the word lines together, a second latch circuit configured to hold an activation/deactivation state of a sense amplifier, a third latch circuit configured to hold a word line activation signal in the operation mode of sequentially activating a plurality of word lines at different times, thereby to activate the word lines together, and a fourth latch circuit configured to hold a signal used to control the state of a row decoder.
According to an aspect of the present invention, there is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a cell array unit are simultaneously activated, comprising an array control circuit which is configured to set the row redundant element into an activated state, set the defective element into a deactivated state and replace the defective element by the row redundant element if at least one of the plurality of elements is defective, the array control circuit including a first latch circuit configured to hold a present state until a precharge command is received if an array control circuit state signal is received in an operation mode of sequentially activating a plurality of word lines at different times, thereby to activate the word lines together, a second latch circuit configured to hold an activation/deactivation state of a sense amplifier, a third latch circuit configured to hold a word line activation signal in the operation mode of sequentially activating a plurality of word lines at different times, thereby to activate the word lines together, and a control circuit configured to control the state of a row decoder.
According to an aspect of the present invention, there is provided a semiconductor storage device in which a plurality of word lines are activated together by causing each of the word lines which is once activated to hold the activated state through a plurality of successive word line selection cycles, comprising a latch circuit which is configured to fetch part of address information to specify a w
Ishizuka Kenji
Kato Daisuke
Taira Takashi
Watanabe Yohji
Hoang Huan
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
LandOfFree
Semiconductor storage device formed to optimize test... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor storage device formed to optimize test..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor storage device formed to optimize test... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3236028