Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2001-04-12
2004-06-15
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S163000, C713S152000, C713S152000
Reexamination Certificate
active
06751716
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device in which fraudulent access and false access are surely prevented, a control device for the semiconductor storage device, and an electronic apparatus which uses the semiconductor storage device.
2. Description of the Related Art
Data stored in a semiconductor storage device may include data which should not be read out or rewritten by an unauthorized person, such as information associated with personal privacy, data protected by copyright, etc. Moreover, in a rewritable semiconductor storage device, such as an EEPROM, stored data may be falsely rewritten due to noises generated by an electronic apparatus or the semiconductor storage device itself, etc. For the purpose of protecting data stored in a memory from unexpected or undesirable access, some semiconductor storage devices and some control devices f or controlling semiconductor storage devices have security circuits incorporated therein.
Hereinafter, a semiconductor storage device having a conventional security function will be described with reference to
FIGS. 13 and 14
.
FIG. 13
is a block diagram showing a primary portion of a conventional semiconductor storage device
1150
. The semiconductor storage device
1150
includes an interface circuit
1103
which communicates with outside, a memory
1109
having a memory space for storing data, and a security circuit
1106
interposed between the interface circuit
1103
and the memory
1109
.
Now, a reading operation in the semiconductor storage device
1150
in which part of the memory space in the memory
1109
is deactivated by the security function is described.
The semiconductor storage device
1150
communicates with the outside through an input bus
1101
and a data input/output bus
1102
connected to the interface circuit
1103
. Through the input bus
1101
, an address for reading data stored in the memory
1109
and a control signal are supplied to the interface circuit
1103
. The interface circuit
1103
analyzes a command input through the input bus
1101
. When the command requests reading of data stored in the memory
1109
, the interface circuit
1103
outputs through an address bus
1104
to the security circuit
1106
an address signal indicating an address in the memory
1109
from which data is to be read out.
The security circuit
1106
determines whether or not the address indicated by the address signal is included in an active memory space from which reading of data is permitted.
When the address indicated by the address signal is included in an active memory space from which reading of data is permitted, the security circuit
1106
supplies the address signal to the memory
1109
through an address bus
1107
according to the address data signal from the interface circuit
1103
and a security setting condition of the security circuit
1106
. The memory
1109
reads out data stored in the address indicated by the address signal, and supplies the data to the security circuit
1106
through a data bus
1108
. The security circuit
1106
supplies the data from the memory
1109
to the interface circuit
1103
, and the interface circuit
1103
outputs the data to the outside through the input/output bus
1102
.
In this way, the semiconductor storage device
1150
normally reads out data stored in the active memory space from which reading of data is permitted.
On the other hand, when an address indicated by the address signal from the interface circuit
1103
is included in an inactive memory space from which reading of data is prohibited, the security circuit
1106
makes any predetermined modification to the address signal, and supplies the modified address signal to the memory
1109
through the address bus
1107
. Alternatively, the security circuit
1106
supplies an address indicated by the address signal from the interface circuit
1103
to the memory
1109
, and receives data in the address from the memory
1109
. Then, the security circuit
1106
makes any predetermined modification to the received data so that the received data is fixed as predetermined data, for example. Alternatively still, both of these modifications are made. By these modifications, the semiconductor storage device
1150
prevents normal reading of data stored in the inactive memory space from which reading of data is prohibited.
As described above, for the purpose of preventing data from being read out when the semiconductor storage device
1150
receives an address signal which commands the semiconductor storage device
1150
to read out data stored in an address in an inactive memory space from which reading of data is prohibited, data to be output is fixed to a predetermined value, for example. There are some other structures therefor where: the security circuit
1106
does not output the address signal to the memory
1109
(Japanese Laid-Open Publication No. 59-152599); the address signal supplied to the memory
1109
is disturbed (Japanese Laid-Open Publication No. 53-225839); data read out from the memory
1109
is disturbed and the disturbed data is output to the interface circuit
1103
through the data bus
1105
(Japanese Laid-Open Publication No. 6-250929).
According to these conventional techniques, any predetermined modification is made to an address signal or a signal transmitted through a data bus, whereby data stored in a memory space of a memory from which reading of data is prohibited is prevented from being normally read out from the memory.
In the example described hereinabove, reading of data is restricted by deactivating the memory space. However, deactivation of the memory space described in the present specification can be employed not only for restricting a reading operation but also for restricting a rewriting operation, restricting a special function allocated to a predetermined address, and restricting some of these operations and functions simultaneously. In either case, restriction is achieved, as in the case of restricting reading of data, by making any predetermined modification to a control signal on an address bus, by making any predetermined modification to data on a data bus, or by making any predetermined modification to other control signals. With such a modification, an active memory space and an inactive memory space are operated in a different manner, i.e., normal operation is performed for an active memory space, and normal operation is hindered for an inactive memory space.
Now, another example of a security function is described with reference to FIG.
14
.
FIG. 14
shows a conventional semiconductor storage device
1250
including an interface circuit
1203
, a security circuit
1206
, and a memory
1209
. In this semiconductor storage device
1250
, a security function is activated at power-on, by inputting a reset signal, etc., and deactivated by inputting a predetermined password inherently given to the semiconductor storage device
1250
.
The security circuit
1206
shown in
FIG. 14
includes a security control circuit
1210
, an operation restriction circuit
1212
for restricting a security function by an output of the security control circuit
1210
. The security control circuit
1210
includes a password storage circuit
1213
and a comparator circuit
1215
for comparing a password supplied from the interface circuit
1203
to the security circuit
1206
with a password stored in the password storage circuit
1213
.
When an externally provided address signal commands the semiconductor storage device
1250
to read out data stored in the memory
1209
, the same operation as in the semiconductor storage device
1150
is performed. That is, when the address signal indicates an address within a memory space from which reading of data is prohibited, the operation restriction circuit
1212
in the security circuit
1206
makes any predetermined modification to the address signal received from the interface circuit
1203
through an address bus
1204
, and the modified address signal is output to the memo
Aikawa Yasuyuki
Sumitani Ken
Takata Hidekazu
Tanaka Yuji
McLean-Mayo Kimberly
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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