Semiconductor storage device and refresh control method thereof

Details Semiconductor storage device and refresh control method thereof Semiconductor storage device and refresh control method thereof

2006-02-28

2006-02-28

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189040

Reexamination Certificate

active

07006401

ABSTRACT:
Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F163is set by a one shot pulse from an OS circuit161, a memory access request is inputted to a memory accessing pulse generator circuit171through a NOR gate167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate168during the memory access, the output of the NOR gate167is at the “L” level, and the refresh request is blocked by the AND gate168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs163, 164and165are reset, the output of the NOR gate167is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit170, and a refresh enable signal RERF is outputted.

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