Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
2000-11-28
2003-06-10
Portka, Gary (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
C711S163000, C711S216000
Reexamination Certificate
active
06578132
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor storage device and a program authenticity determining system using the same. More specifically, the present invention relates to a semiconductor storage device such as a ROM which stores a program in, for example, a cartridge for a game machine, and an authenticity determining system for the program.
BACKGROUND AND SUMMARY OF THE INVENTION
A cartridge (for example) for a game machine includes a semiconductor storage device such as a ROM in which a game program is written, and is attached, while in use, to a game machine body. Especially, in the case of a popular cartridge, the market is often infested with non-authentic imitations where the game program is unlawfully copied.
As disclosed in Japanese Patent Laying-open No. 2-31256 [G06F 12/14], the applicant proposed an “Address Decoding” system capable of preventing the game program and other programs from being unlawfully copied or the data from being changed by determining the authenticity of a cartridge and by inhibiting access to a program memory where the cartridge is not authentic.
In the above-described prior art, by using an “Address Decoding Method”, the authenticity is determined in accordance with program data actually read from the program memory, and therefore, it is possible to remove the imitations with a high degree of reliability. However, in the above-described prior art, it is necessary to decode a number of addresses. In such a system, if the addresses to be decoded are analyzed by a copyist, the protective effect against the unlawful utilization of the program may be lost.
SUMMARY OF THE INVENTION
Therefore, a principal feature of the illustrative embodiments is to provide a novel semiconductor storage device and a program authenticating system using the same.
Another feature of the illustrative embodiments of the present invention is to provide a semiconductor storage device capable of making an analysis of a program more difficult and providing a lasting protective effect, and to provide a program authenticating system using the same.
A semiconductor storage device according to the illustrative embodiments of the present invention is a semiconductor storage device in which program data to be executed by a central processing unit is fixedly stored and which outputs the program data from addresses designated by address data, comprising: a program data store for fixedly storing the program data; a code generator for generating an address calculation code; and an address processing circuitry which receives first address data output from the central processing unit, wherein the address processing circuitry outputs new second address data obtained by performing calculation on at least a portion of the first address data on the basis of the address calculation code at a time that a control signal exists and applies the second address data to the program data storing means, and applies the first address data to the program data store at a time that no control signal exists.
Specifically, the address processing circuitry includes calculating circuitry capable of outputting the second address data by calculating at least the portion of the first address data by using the address calculation code, and a selector which outputs the second address data when the control signal is applied to the selector and outputs the first address data when the control signal is not applied to the selector.
The calculating circuitry may include a plurality of calculators capable of performing different kinds of calculations, respectively and thus outputting different kinds of second address data, respectively on reception of the first address data and the address calculation code, and the code generator further generates a calculator selection code by which any one of the plurality of calculators can be selected, and the selector may select the second address data associated with the calculator selected by the calculator selecting code, or the first address data.
In accordance with one aspect of the illustrative embodiments, a semiconductor storage device comprises a program data store for fixedly storing program data; a code generator for generating an address calculation code; and address processing circuitry which receives first address data output from a central processing unit, wherein the address processing circuitry outputs new second address data obtained by performing a first calculation on at least a portion of the first address data based upon the address calculation code at a time that a control signal exists and applies the second address data to the program data storing means, and outputs new third address data obtained by performing a second calculation different from the first calculation on at least a portion of the first address data based upon the address calculation code at a time that no control signal exists and applies the third address data to the program data store.
One of the first calculation and the second calculation performed by the address processing circuitry converts the first address data into address data for outputting program data that is to be regularly executed by the central processing unit.
A program discrimination system according to an illustrative embodiment comprises a read-only program storage unit which fixedly stores program data and a central processing unit which executes the program data by reading the program data from the program storage unit and determines whether or not the program is a regular, authentic program, and wherein the program storage unit includes a program data store for fixedly storing the program data, a code generator for generating an address calculation code, and address processing circuitry for receiving first address data output from the central processing unit, wherein the address processing circuitry outputs new second address data obtained by performing a calculation on at least a portion of the first address data based upon the address calculation code when a control signal is applied from the central processing unit and applies the second address data to the program data store, and applies the first address data to the program data store when no control signal is applied, and the central processing unit including control signal applying circuitry for applying the control signal to the address processing circuitry of the program storage unit, an address output circuit for outputting the first address data to apply the first address data to the address processing circuitry just after the control signal is applied, and a circuitry for determining the authenticity of the program storage unit by determining whether or not a predetermined relationship exists between the program data read from the program data storing means in accordance with the second address data and check data that is set in advance.
The central processing unit further includes a program terminator for forcedly terminating the program when the determined result indicates a false program storage unit.
In the semiconductor storage device, when the control signal which is output from the central processing unit in response to specific program data read from the program data store is applied to the address processing circuitry, the address processing circuitry outputs the second address data by performing a calculation on all bits or a subset thereof of the first address data based upon the address calculation code from the code generator and applies the second address data to the program data storing means. Specifically, the calculating circuitry of the address processing circuitry calculates the first address data by using the address calculation code so as to output the second address data, and the selector outputs the second address data in response to the control signal. Therefore, from the program data storing circuitry, in response to the control signal, the program data is read from an address that is designated by not the first address data output from the central processing unit but the second address da
Nintendo Co. Ltd.
Nixon & Vanderhye P.C.
Portka Gary
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