Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-06-01
2003-04-29
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S203000
Reexamination Certificate
active
06556491
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor storage device, i.e., a dynamic random access memory (DRAM), suitable for testing a charge-holding time of a memory cell of in a short time, and to a method of testing the storage device.
BACKGROUND OF THE INVENTION
A capacity of a semiconductor storage device increases recently along with a progress in a large scale integration technology, and requires a longer test time. A system large scale integrated circuit (LSI) is further advanced in function and complicated. It is hence an important problem how to shorten the test time of the LSI to enhance the test efficiency and reduce the manufacturing cost.
A semiconductor storage device is tested under various test patterns in order to test whether the memory cell, a storage unit in the storage device, can be read and written correctly. A dynamic random access memory (DRAM) particularly includes a memory cell having volatile data, thus being tested whether the holding time of an electric charge stored in the memory cell satisfies the specification or not (a charge-holding characteristic). Therefore, for the DRAM, the charge-holding characteristic is generally tested.
FIG. 6
shows a circuit configuration of the memory cell of an ordinary DRAM, which consists of a single transistor and a single capacitor. In the diagram, the memory cell includes a memory cell capacitor (MC), a memory cell transistor (TWL), a word line (WL), a bit line (BL). A potential (VCP) is applied to a plate electrode of the memory cell capacitor. The plate electrode is an opposite electrode connected to the memory cell transistor.
The DRAM shown in
FIG. 6
stores data with a small electric charge stored in the memory cell capacitor (MC). The stored charge disappears gradually due to a small leak current. The leak current may flow various routes. A leak current (A) flows to the plate electrode through an insulating film of the memory cell capacitor. A leak current (B) flows from a diffusion layer of the memory cell transistor to a semiconductor substrate. A leak current (C) flows through a gate insulating film of the memory cell transistor to the gate (the word line). A leak current (D) flows to an adjacent memory cell. A leak current (E) flows to the bit line through the memory cell transistor (a cut-off current between a drain and a source of the transistor). Methods for detecting these leak currents are required.
To test the charge-holding time of the DRAM, following method is usually employed:
1) Write data into all memory cells in a writing cycle;
2) Then, leave the cells for a specific time (a stand-by period); and
3) Then, read the data in a reading cycle.
The method enables defects due to the leak currents (A) through (C) to be detected. Modifying a writing pattern to, for example, a checker pattern enables defects due to the leak current (D) to be detected. For detecting defects due to the leak current (E), during the standby period, the potential of the bit line is set to that corresponding to an opposite logic against the stored data in the memory cell capacitor (MC). And thus, the voltage between the memory cell capacitor (MC) and bit line may be applied between the drain and the source of the memory cell transistor.
For example, data “1” is written in the memory cell capacitor (MC). Then, the word line is set in non-selected state, and a potential of data “0”, an opposite data against data written in the memory cell, is applied to the bit line (BL), and this state is left for a specific time. Then, the data is read out, and it is tested whether the written data “1” is eliminated or not.
A circuit configuration of the conventional DRAM and a test method for realizing the above way will be explained below with referring to the drawings.
FIG. 7
shows a peripheral circuit of a memory cell array of the conventional DRAM. In
FIG. 7
, a memory cell array
1
includes memory cells
2
arranged in matrix. A pair of bit lines
3
(BL) and
4
(NBL) are connected to a sense amplifier (Amp)
5
. When a sense-Amp-activating signal
13
(SE) starts (turns to a high (H) level), a sense-Amp driver
101
sets a node
102
(SAN) to a ground potential (0V) and sets a node
103
(SAP) to a supply voltage (VDD). Then, the sense amplifier
5
amplifies the potential between the pair of the bit lines. The drain of the memory cell transistor is connected to one of the bit lines, and the gate of the transistor is connected to a word line
6
. A bit line pre-charge equalizer
7
sets the pair of the bit lines
3
(BL) and
4
(NBL) to a reference voltage
11
(VBP), for example, ½VDD, generated by a reference voltage generator
9
when a pre-charge signal
8
is activated and set to the H level.
FIG. 8
shows a reference voltage generator for generating the reference voltage of ½VDD. If a resistance
104
(R
1
) and a resistance
105
(R
2
) are sufficiently large, the voltage at a node
106
(N) equal to ½VDD. Voltages at a node
107
(NA) and a node
108
(NB) are equal to (VDD/2)+Vt and (VDD/2)−Vt, respectively, where the “Vt” is a threshold voltage of all transistors. And then an output voltage Vout of a node
106
is stabilized at ½VDD.
A method of testing a charge-holding characteristic regarding a leak to the bit line for a conventional circuit will be explained with referring to FIG.
7
. First, data “1”, i.e., data for storing a charge in the memory cell capacitor (MC) is written in each memory cell. Then, the word line
6
is activated, and the data in the memory cell connected to the word line
6
(WL
0
) is read out. As a result, for example, the bit line
4
(NBL) is set to data of “1” by the data read out and amplified by the sense amplifier
5
, and the data of the bit line
3
(BL) is set to “0”. That is, the bit line
3
(BL) pairing with the bit line
4
(NBL) is set to the opposite data of that of the memory cell. And with repeating reading the data for a specific time, the charge-holding characteristic of the memory cell connected to the bit line
3
(BL) is tested. That is, the charge-holding characteristic is tested because the data of the memory cell is set to data of “1” and the data of the bit line
3
(BL) is set to “0”. After repeating reading the data for a specific time, the data of “1” written in each memory cell is read out. Then, after writing data of “1” in each memory cell again, and then, with activating a word line
60
(WL
1
), the charge-holding characteristic of the other bit line
4
(NBL) pairing with the bit line
3
(BL) is similarly tested. Therefore, the same as the above, after activating the word line
60
(WL
1
) and repeating reading data for a specific time, with reading the data “1” written in each memory cell, the charge-holding characteristic regarding a leak to the bit line
4
(NBL) in a whole memory is be tested.
A method of testing the charge-holding characteristic of a memory is proposed, for example, in Japanese Patent Laid-open No. 11-154400. The publication discloses an apparatus for applying a voltage corresponding to data written from the outside to a bit line pair by deactivating a word line in a test mode.
FIG. 9
shows a specific circuit in which data entering from an input/output terminal
110
(I/O) is put into a write amplifier
111
, and written into a memory cell
2
through a column selector
112
, a pre-charge equalizer
7
, and a sense amplifier
5
.
Receiving the data from the input/output terminal
110
(I/O), the circuit transmits opposite data in a pair of bit lines
3
(BL) and
4
(NBL) to each other. For example, when the bit line
3
(BL) is set to “1”, the bit line
4
(NBL) is set to “0”. When the word line is deactivated in a test mode, when data is entered from the input/output terminal
110
(I/O), opposite potentials are applied to the bit lines
3
(BL) and
4
(NBL), and thus, all bit lines can not be set to the same level simultaneously.
Therefore, to test the charge-holding characteristic regarding a leak to the bit line, it is required to dividing the test procedure in
Otsuka Hidefumi
Yamasaki Yuji
Lam David
Matsushita Electric - Industrial Co., Ltd.
RatnerPrestia
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