Semiconductor storage device and method of selecting bit...

Details Semiconductor storage device and method of selecting bit... Semiconductor storage device and method of selecting bit...

2007-03-13

2007-03-13

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S230010, C365S230060

Reexamination Certificate

active

11155510

ABSTRACT:
Of bit line selection address bits A(k) to A(k+3), address bits A(k+1) and A(k+2) are subjected to exclusive OR operation with address bit A(k+3) by an address conversion circuit20,and when address bit A(k+3) is at high level, the address is inputted to an upper column decoder11with their logical levels inverted. In left and right areas AA0and AA1of eight bit lines within subarray AA, the order of selecting bit lines is switched in ascending order and descending order every four lines. With the construction of a lower pass gate220that alternately selects the left and right areas AA0and AA1for each access, in continuous access within subarray and between subarrays, the distance between bit lines selected in adjacent accesses can be sufficiently secured, so that the electrical influence of a bit line accessed previously exerts no influence on a bit line accessed subsequently.

REFERENCES:
patent: 2002/0062433 (2002-05-01), Suzuki
patent: 2003/0103396 (2003-06-01), Maruyama et al.
patent: 09-245493 (1997-09-01), None
patent: 10-069773 (1998-03-01), None
patent: 11-086558 (1999-03-01), None
patent: 2000-132985 (2000-05-01), None
patent: 2001-256789 (2001-09-01), None
patent: 2003-162897 (2003-06-01), None

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