Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2007-01-02
2007-01-02
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S185250, C365S189070, C365S230060
Reexamination Certificate
active
11097247
ABSTRACT:
A semiconductor storage device having a memory cell array in which a plurality of memory cells is provided at intersections of a plurality of bit lines and a plurality of word lines and executing refreshing for holding data, including: memory cells for pairing provided on the memory cell array, for compensating for errors of each memory cell; a control circuit for checking a data holding ability of memory cell under test in a predetermined period after power-on; a storage circuit for storing information which specifies the memory cells under test for which it is determined that the data holding ability is low in the checking of the control circuit; and a selecting-line activating circuit for activating circuit for activating a selecting line for pairing corresponding to the memory cells for pairing based on a result of comparing a specific address to be input with the information stored in the storage circuit.
REFERENCES:
patent: 5453959 (1995-09-01), Sakuta et al.
patent: 6728156 (2004-04-01), Kilmer et al.
patent: 6751144 (2004-06-01), Takahashi et al.
patent: 6-203596 (1994-07-01), None
Ito Yutaka
Riho Yoshiro
Elms Richard
Elpida Memory Inc.
Le Toan
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