Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2005-01-25
2005-01-25
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S230060
Reexamination Certificate
active
06847563
ABSTRACT:
A semiconductor storage device and a method for correcting defects of memory cells, in which the semiconductor storage device has a memory cell array provided with a normal memory cell area and a redundant memory cell area. A test is conducted in the semiconductor storage device to check whether or not a defect of a memory cell exists in the normal memory cell area and/or redundant memory cell area and in which defective memory cell columns or defective memory cell rows in the normal memory cell area are replaced with redundant memory cell columns or redundant memory cell rows. In the semiconductor storage, in the test conducted on the redundant memory cell area, if redundant memory cell columns or redundant memory cell rows have already been replaced, judgment is made to exclude the redundant memory cell columns or redundant memory cell rows from the columns or rows respectively to be replaced.
REFERENCES:
patent: 6023433 (2000-02-01), Koshikawa
patent: 6160745 (2000-12-01), Hashimoto
Elpida Memory Inc.
Lam David
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