Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-08-30
2011-08-30
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S723000, C714S736000
Reexamination Certificate
active
08010853
ABSTRACT:
Each of a plurality of nonmatching detection circuits is provided for each bit, compares bit output of memory with an expected value corresponding to the bit output, and outputs a nonmatching detection signal when the bit output does not match the value. A selection circuit selects and outputs the output of one or more nonmatching detection circuits in the plurality of nonmatching detection circuits. When the selection circuit outputs at least one nonmatching detection signal, a nonmatching result holding circuit holds the value of the nonmatching detection signal.
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Notice of Rejection Grounds for corresponding Japanese patent application No. 2005-289044, mailed Apr. 12, 2011.
Fujitsu Semiconductor Ltd.
Gaffin Jeffrey A
McMahon Daniel
Staas & Halsey , LLP
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