Semiconductor storage device and memory cell test method

Details Semiconductor storage device and memory cell test method Semiconductor storage device and memory cell test method

2011-03-08

2011-03-08

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S185090, C365S230060

Reexamination Certificate

active

07903482

ABSTRACT:
A semiconductor storage device includes: a memory section including memory cell groups; a redundancy circuit which stops to access the memory section when the redundancy circuit section is activated, and to activate one of the redundancy memory cell groups corresponding to an address signal when the redundancy circuit section is activated; a redundancy decoder which accesses one of the redundancy memory cell groups corresponding to an input selection signal; and a decoder which accesses one of the memory cell groups corresponding to an input address signal, and stops to access the memory cell groups in response to a selection signal. In a normal mode, an access to the redundancy memory section is permitted. In a redundancy circuit inactivation mode, an access to the redundancy memory section is prohibited. Memory tests of a storage device under various conditions can be performed in a short time.

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