Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2002-12-02
2004-06-15
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S210130, C365S230060
Reexamination Certificate
active
06751131
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory in which data is electrically rewritable, e.g., a semiconductor storage device such as a flash EEPROM or the like, and to an information device using the non-volatile memory, such as a cellular phone terminal or the like.
2. Description of the Related Art
Conventionally, in a non-volatile semiconductor storage device (a non-volatile memory) in which data is electrically rewritable, e.g., a flash EEPROM, a data read operation is performed as follows: as shown in
FIG. 8
, the same drain voltage is applied to a memory cell RC
0
set at a predetermined threshold value, which is called a “reference cell”, and to a memory cell MC
0
of a memory array on which a data read operation is performed, while the same gate voltage is applied by a reference word line decoder and a normal word line decoder, and a difference between the values of currents flowing through the memory cells RC
0
and MC
0
is amplified by a sense amplifier S/A, and the result of the amplification is read out as stored data.
In a conventional method for applying a gate voltage to a reference cell RC
0
, a gate voltage is constantly applied to the reference cell RC
0
while the supply voltage is supplied to the storage device (see FIGS.
9
through
11
). In another conventional method, a gate voltage is applied to the reference cell RC
0
according to an ATD signal which is activated during the data read operation (see FIGS.
12
through
14
). Each of these methods will be specifically described below.
FIG. 9
is a block diagram showing an exemplary structure of a primary part of a conventional non-volatile semiconductor storage device
10
.
FIG. 9
illustrates a method wherein a voltage is constantly applied to each of the word lines of reference cells RC
0
, RC
1
and RC
2
while the supply voltage is supplied to the storage device.
In
FIG. 9
, the conventional non-volatile semiconductor storage device
10
includes: a memory cell array RA formed by a plurality of reference cells RC
0
-RC
2
(hereinafter, referred to as “reference array RA”): level shifters LS
0
and LS
1
, which form a word line control circuit for controlling the word lines of the reference cells; a memory cell array MA (hereinafter, referred to as “memory array MA”), which is a data storage region; a normal word line predecoder XPDEC; a normal word line decoder XDEC; a redundant word line predecoder XPRDEC; and a redundant word line decoder XRDEC.
The reference array RA includes: the reference cell RC
0
used in a data read operation; the reference cell RC
1
used for verifying deletion of data; and the reference cell RC
2
used for verification in a data write operation. A reference cell word line RWL
0
is connected to the gates of the reference cells RC
0
and RC
1
, and a reference cell word line RWL
1
is connected to the gate of the reference cell RC
2
. A bit line RBL
0
is connected to the drain of the reference cell RC
0
; a bit line RBL
1
is connected to the drain of the reference cell RC
1
; and a bit line RBL
2
is connected to the drain of the reference cell RC
2
. The sources of the reference cells RC
0
-RC
2
are all connected to a common source line RHS.
The level shifters LS
0
and LS
1
are powered by a node voltage HWL for word lines. The level shifter LS
0
receives a reference cell selection signal SEL
0
, and outputs a voltage based on the received reference cell selection signal SEL
0
to the reference cell word line RWL
0
, thereby selecting the word line RWL
0
. The level shifter LS
1
receives a reference cell selection signal SEL
1
, and outputs a voltage based on the received reference cell selection signal SEL
1
to the reference cell word line RWL
1
, thereby selecting the word line RWL
1
. The reference cell selection signals SEL
0
and SEL
1
are exclusively activated, such that one of the signals SEL
0
and SEL
1
is ON (e.g., when the supply voltage VCC is supplied to the storage device
10
) while the other is OFF. For example, when the reference cell selection signal SEL
0
is ON, the potential of the reference cell word line RWL
0
rises, whereby the reference cell word line RWL
0
is selected. When the reference cell selection signal SEL
1
is ON, the potential of the reference cell word line RWL
1
rises, whereby the reference cell word line RWL
1
is selected.
The memory array MA includes a plurality of memory cells as memory elements arranged in a matrix along row and column directions. Herein, the description is simplified by referring only to memory cells MC
0
and MC
1
of the memory array MA. A memory array normal word line MWL is connected to the gate of the memory cell MC
0
, and a memory array redundant word line ReWL is connected to the gate of the memory cell MC
1
. A common bit line MBL is connected to each of the drains of the memory cells MC
0
and MC
1
, and a source line MHS is connected to each of the sources of the memory cells MC
0
and MC
1
. The source lines RHS and MHS are generally kept at the ground level, but controlled to be at a different level when the storage device is in a special mode, such as a test mode or the like. For example, in a deletion mode, the source lines RHS and MHS are at a high voltage level.
A redundancy determination signal MD, an address signal ADD and a word line enabling ATD signal SPW are input to the normal word line predecoder XPDEC. Based on these signals, the normal word line predecoder XPDEC outputs a normal word line selection signal SX to the normal word line decoder XDEC.
The normal word line decoder XDEC is powered by the node voltage HWL for word lines. Further, the normal word line decoder XDEC receives a normal word line selection signal SX which is output from the normal word line predecoder XPDEC, and outputs a voltage to a predetermined memory array normal word line MWL according to the normal word line selection signal SX, thereby selecting the predetermined memory array normal word line MWL.
The redundant word line predecoder XPRDEC receives the address signal ADD, the word line enabling ATD signal SPW, and a redundant word line address signal BADD. According to these signals, the redundant word line predecoder XPRDEC outputs a redundancy determination signal MD to the normal word line predecoder XPDEC, and a redundant word line selection signal RX to the redundant word line decoder XRDEC.
The redundant word line decoder XRDEC is powered by the node voltage HWL for word lines. Further, the redundant word line decoder XRDEC receives a redundant word line selection signal RX which is output from the redundant word line predecoder XPRDEC, and outputs a voltage to a predetermined memory array redundant word line ReWL according to the redundant word line selection signal RX, thereby selecting the predetermined memory array redundant word line ReWL.
A word line selection operation is now described with reference to the timing chart of
FIG. 10
, which is performed by a word line control circuit for the reference cells, a normal word line control circuit for the memory array, and a redundant word line control circuit for the memory array when a non-redundant memory array normal word line is selected.
FIG. 10
shows, from the top to the bottom of
FIG. 10
, supply voltage VCC; the node voltage HWL for word lines; a chip enabling signal CE# which is a control signal for activating the storage device
10
; an output enabling signal OE# which is a control signal for permitting data output; the word line enable ATD signal SPW which is output from an address transition detection circuit (not shown); the potential of the reference cell word line RWL
0
; the normal word line selection signal SX; the potential of the memory array normal word line MWL; and the potential of the memory array redundant word line ReWL. When both the chip enabling signal CE# and the output enabling signal OE# are at the ground level, a data read operation can be performed. The chip enabling signal CE# and the output enabling signal OE# are
Lam David
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
LandOfFree
Semiconductor storage device and information apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor storage device and information apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor storage device and information apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3298944