Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-07-14
2000-03-28
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, 36523006, G11C 700
Patent
active
060440287
ABSTRACT:
A semiconductor storage device which can prevent a short-circuit current from flowing therethrough even if a short circuit occurs between main word lines and bit lines. The semiconductor storage device has a plurality of normal memory cell array blocks, each including multiple columns of bit line pairs, sub word lines and normal memory cells. The semiconductor storage device also includes main word lines extending through the plurality of normal memory cell array blocks, a main row selecting decoder for selecting one of the main word lines on the basis of a main row address signal, a sub row selecting decoder for selecting one of the sub word lines depending on one of the main word lines on the basis of a sub row address signal, and a pre-charge circuit for pre-charging a pair of bit lines. The main row selecting decoder has a first setting circuit for inactivating the main word line at a high level potential substantially equal to a potential of a pre-charged bit line pair, while at a low level potential, the main word line is activated. The sub row selecting decoder has a second setting circuit for inactivating the sub word lines when the main word line is in the high level potential. The second setting circuit has an inverting element for receiving and inverting a signal from the main word line, the inverted signal being then outputted therefrom, and a switch for inactivating the sub word lines when the output of the inverting element is in the low level potential.
REFERENCES:
patent: 4747082 (1988-05-01), Minato
Kumagai Takashi
Tomohiro Yasuhiko
Seiko Epson Corporation
Zarabian A.
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