Semiconductor storage device

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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Reexamination Certificate

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11318776

ABSTRACT:
The SRAM cell1includes inverters10, 20, N-type FETs (Field Effect Transistors)32, 34, 36, 38, word lines42, 44, and bit lines46, 48. A gate width W2and gate length L2of the FETs32, 34, 36, 38are equal to a gate width W3and gate length L3of the FETs12, 22, respectively. In particular, in this embodiment, a gate width W4and gate length L4of the FETs14, 24are also equal to W2(=W3) and L2(=L3), respectively. Namely, the SRAM cell1is designed in such a manner that W2=W3=W4, and L2=L3=L4.

REFERENCES:
patent: 6091626 (2000-07-01), Madan
patent: 7164596 (2007-01-01), Deng et al.
patent: 08-0007574 (1996-01-01), None
patent: 11-007776 (1996-01-01), None

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